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<h1><a name="Message">Timing Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Timing Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>F:\code\fpga\MIC_HDMI_FINISHED\impl\gwsynthesis\top.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>F:\code\fpga\MIC_HDMI_FINISHED\src\top.cst</td>
</tr>
<tr>
<td class="label">Timing Constraint File</td>
<td>F:\code\fpga\MIC_HDMI_FINISHED\src\lcd.sdc</td>
</tr>
<tr>
<td class="label">Version</td>
<td>V1.9.8.07</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Sun Nov 20 04:37:03 2022
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="Summary">Timing Summaries</a></h1>
<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Setup Delay Model</td>
<td>Slow 0.95V 85C C8/I7</td>
</tr>
<tr>
<td class="label">Hold Delay Model</td>
<td>Fast 1.05V 0C C8/I7</td>
</tr>
<tr>
<td class="label">Numbers of Paths Analyzed</td>
<td>29681</td>
</tr>
<tr>
<td class="label">Numbers of Endpoints Analyzed</td>
<td>19849</td>
</tr>
<tr>
<td class="label">Numbers of Falling Endpoints</td>
<td>29</td>
</tr>
<tr>
<td class="label">Numbers of Setup Violated Endpoints</td>
<td>1679</td>
</tr>
<tr>
<td class="label">Numbers of Hold Violated Endpoints</td>
<td>131</td>
</tr>
</table>
<h2><a name="Clock_Report">Clock Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Type</th>
<th class="label">Period</th>
<th class="label">Frequency(MHz)</th>
<th class="label">Rise</th>
<th class="label">Fall</th>
<th class="label">Source</th>
<th class="label">Master</th>
<th class="label">Objects</th>
</tr>
<tr>
<td>clk</td>
<td>Base</td>
<td>37.037</td>
<td>27.000
<td>0.000</td>
<td>18.518</td>
<td></td>
<td></td>
<td>clk </td>
</tr>
<tr>
<td>cmos_pclk</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>cmos_pclk </td>
</tr>
<tr>
<td>cmos_vsync</td>
<td>Base</td>
<td>1000.000</td>
<td>1.000
<td>0.000</td>
<td>500.000</td>
<td></td>
<td></td>
<td>cmos_vsync </td>
</tr>
<tr>
<td>mem_clk</td>
<td>Base</td>
<td>2.500</td>
<td>400.000
<td>0.000</td>
<td>1.250</td>
<td></td>
<td></td>
<td>memory_clk </td>
</tr>
<tr>
<td>max_finish</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>max_sample_inst/max_finish_s0/Q </td>
</tr>
<tr>
<td>cmos_16bit_clk</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>cmos_8_16bit_m0/de_o_s0/Q </td>
</tr>
<tr>
<td>mic_clk_d</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_1_s0/Q </td>
</tr>
<tr>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_1_s0/Q </td>
</tr>
<tr>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_0[1]</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_1_s0/Q </td>
</tr>
<tr>
<td>steer_inst1/clk_50hz_6</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>steer_inst1/clk_50hz_s2/Q </td>
</tr>
<tr>
<td>steer_inst2/clk_50hz_6</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>steer_inst2/clk_50hz_s2/Q </td>
</tr>
<tr>
<td>cmos_pll_m0/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>41.667</td>
<td>24.000
<td>0.000</td>
<td>20.833</td>
<td>gowin_ibuf_clk/I</td>
<td>clk</td>
<td>cmos_pll_m0/rpll_inst/CLKOUT </td>
</tr>
<tr>
<td>cmos_pll_m0/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Generated</td>
<td>41.667</td>
<td>24.000
<td>0.000</td>
<td>20.833</td>
<td>gowin_ibuf_clk/I</td>
<td>clk</td>
<td>cmos_pll_m0/rpll_inst/CLKOUTP </td>
</tr>
<tr>
<td>cmos_pll_m0/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Generated</td>
<td>83.333</td>
<td>12.000
<td>0.000</td>
<td>41.667</td>
<td>gowin_ibuf_clk/I</td>
<td>clk</td>
<td>cmos_pll_m0/rpll_inst/CLKOUTD </td>
</tr>
<tr>
<td>cmos_pll_m0/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Generated</td>
<td>125.000</td>
<td>8.000
<td>0.000</td>
<td>62.500</td>
<td>gowin_ibuf_clk/I</td>
<td>clk</td>
<td>cmos_pll_m0/rpll_inst/CLKOUTD3 </td>
</tr>
<tr>
<td>mem_pll_m0/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Generated</td>
<td>2.511</td>
<td>398.250
<td>0.000</td>
<td>1.255</td>
<td>gowin_ibuf_clk/I</td>
<td>clk</td>
<td>mem_pll_m0/rpll_inst/CLKOUTP </td>
</tr>
<tr>
<td>mem_pll_m0/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Generated</td>
<td>5.022</td>
<td>199.125
<td>0.000</td>
<td>2.511</td>
<td>gowin_ibuf_clk/I</td>
<td>clk</td>
<td>mem_pll_m0/rpll_inst/CLKOUTD </td>
</tr>
<tr>
<td>mem_pll_m0/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Generated</td>
<td>7.533</td>
<td>132.750
<td>0.000</td>
<td>3.766</td>
<td>gowin_ibuf_clk/I</td>
<td>clk</td>
<td>mem_pll_m0/rpll_inst/CLKOUTD3 </td>
</tr>
<tr>
<td>u_tmds_rpll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>3.086</td>
<td>324.000
<td>0.000</td>
<td>1.543</td>
<td>gowin_ibuf_clk/I</td>
<td>clk</td>
<td>u_tmds_rpll/rpll_inst/CLKOUT </td>
</tr>
<tr>
<td>u_tmds_rpll/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Generated</td>
<td>3.086</td>
<td>324.000
<td>0.000</td>
<td>1.543</td>
<td>gowin_ibuf_clk/I</td>
<td>clk</td>
<td>u_tmds_rpll/rpll_inst/CLKOUTP </td>
</tr>
<tr>
<td>u_tmds_rpll/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Generated</td>
<td>6.173</td>
<td>162.000
<td>0.000</td>
<td>3.086</td>
<td>gowin_ibuf_clk/I</td>
<td>clk</td>
<td>u_tmds_rpll/rpll_inst/CLKOUTD </td>
</tr>
<tr>
<td>u_tmds_rpll/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Generated</td>
<td>9.259</td>
<td>108.000
<td>0.000</td>
<td>4.630</td>
<td>gowin_ibuf_clk/I</td>
<td>clk</td>
<td>u_tmds_rpll/rpll_inst/CLKOUTD3 </td>
</tr>
<tr>
<td>u_clkdiv/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>15.432</td>
<td>64.800
<td>0.000</td>
<td>7.716</td>
<td>u_tmds_rpll/rpll_inst/CLKOUT</td>
<td>u_tmds_rpll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>u_clkdiv/CLKOUT </td>
</tr>
<tr>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td>mem_pll_m0/rpll_inst/CLKOUT</td>
<td>mem_clk</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT </td>
</tr>
</table>
<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
<table>
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>clk</td>
<td>27.000(MHz)</td>
<td>28.451(MHz)</td>
<td>11</td>
<td>TOP</td>
</tr>
<tr>
<td>2</td>
<td>cmos_pclk</td>
<td>100.000(MHz)</td>
<td>390.988(MHz)</td>
<td>1</td>
<td>TOP</td>
</tr>
<tr>
<td>3</td>
<td>mem_clk</td>
<td>400.000(MHz)</td>
<td>2016.129(MHz)</td>
<td>1</td>
<td>TOP</td>
</tr>
<tr>
<td>4</td>
<td>cmos_16bit_clk</td>
<td>100.000(MHz)</td>
<td>163.720(MHz)</td>
<td>6</td>
<td>TOP</td>
</tr>
<tr>
<td>5</td>
<td>mic_clk_d</td>
<td>100.000(MHz)</td>
<td>831.131(MHz)</td>
<td>1</td>
<td>TOP</td>
</tr>
<tr>
<td>6</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
<td>100.000(MHz)</td>
<td>771.569(MHz)</td>
<td>1</td>
<td>TOP</td>
</tr>
<tr>
<td>7</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_0[1]</td>
<td>100.000(MHz)</td>
<td>592.193(MHz)</td>
<td>1</td>
<td>TOP</td>
</tr>
<tr>
<td>8</td>
<td>steer_inst1/clk_50hz_6</td>
<td>100.000(MHz)</td>
<td>133.287(MHz)</td>
<td>9</td>
<td>TOP</td>
</tr>
<tr>
<td>9</td>
<td>steer_inst2/clk_50hz_6</td>
<td>100.000(MHz)</td>
<td>110.541(MHz)</td>
<td>12</td>
<td>TOP</td>
</tr>
<tr>
<td>10</td>
<td>u_clkdiv/CLKOUT.default_gen_clk</td>
<td>64.800(MHz)</td>
<td style="color: #FF0000;">10.202(MHz)</td>
<td>95</td>
<td>TOP</td>
</tr>
<tr>
<td>11</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
<td>100.000(MHz)</td>
<td style="color: #FF0000;">94.260(MHz)</td>
<td>10</td>
<td>TOP</td>
</tr>
</table>
<h4>No timing paths to get frequency of cmos_vsync!</h4>
<h4>No timing paths to get frequency of max_finish!</h4>
<h4>No timing paths to get frequency of cmos_pll_m0/rpll_inst/CLKOUT.default_gen_clk!</h4>
<h4>No timing paths to get frequency of cmos_pll_m0/rpll_inst/CLKOUTP.default_gen_clk!</h4>
<h4>No timing paths to get frequency of cmos_pll_m0/rpll_inst/CLKOUTD.default_gen_clk!</h4>
<h4>No timing paths to get frequency of cmos_pll_m0/rpll_inst/CLKOUTD3.default_gen_clk!</h4>
<h4>No timing paths to get frequency of mem_pll_m0/rpll_inst/CLKOUTP.default_gen_clk!</h4>
<h4>No timing paths to get frequency of mem_pll_m0/rpll_inst/CLKOUTD.default_gen_clk!</h4>
<h4>No timing paths to get frequency of mem_pll_m0/rpll_inst/CLKOUTD3.default_gen_clk!</h4>
<h4>No timing paths to get frequency of u_tmds_rpll/rpll_inst/CLKOUT.default_gen_clk!</h4>
<h4>No timing paths to get frequency of u_tmds_rpll/rpll_inst/CLKOUTP.default_gen_clk!</h4>
<h4>No timing paths to get frequency of u_tmds_rpll/rpll_inst/CLKOUTD.default_gen_clk!</h4>
<h4>No timing paths to get frequency of u_tmds_rpll/rpll_inst/CLKOUTD3.default_gen_clk!</h4>
<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Analysis Type</th>
<th class="label">Endpoints TNS</th>
<th class="label">Number of Endpoints</th>
</tr>
<tr>
<td>clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>cmos_pclk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>cmos_pclk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>cmos_vsync</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>cmos_vsync</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>mem_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>mem_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>max_finish</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>max_finish</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>cmos_16bit_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>cmos_16bit_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>mic_clk_d</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>mic_clk_d</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_0[1]</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_0[1]</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>steer_inst1/clk_50hz_6</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>steer_inst1/clk_50hz_6</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>steer_inst2/clk_50hz_6</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>steer_inst2/clk_50hz_6</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>cmos_pll_m0/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>cmos_pll_m0/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>cmos_pll_m0/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>cmos_pll_m0/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>cmos_pll_m0/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>cmos_pll_m0/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>cmos_pll_m0/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>cmos_pll_m0/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>mem_pll_m0/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>mem_pll_m0/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>mem_pll_m0/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>mem_pll_m0/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>mem_pll_m0/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>mem_pll_m0/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_tmds_rpll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_tmds_rpll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_tmds_rpll/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_tmds_rpll/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_tmds_rpll/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_tmds_rpll/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_tmds_rpll/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_tmds_rpll/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_clkdiv/CLKOUT.default_gen_clk</td>
<td>Setup</td>
<td>-1165.370</td>
<td>16</td>
</tr>
<tr>
<td>u_clkdiv/CLKOUT.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
<td>Setup</td>
<td>-3.455</td>
<td>12</td>
</tr>
<tr>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
</table>
<h1><a name="Detail">Timing Details</a></h1>
<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
<h4>Report Command:report_timing -setup -from_clock [get_clocks {clk*}] -to_clock [get_clocks {clk*}] -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>0.944</td>
<td>Gowin_PicoRV32_Top_inst/rstdly_15_s1/Q</td>
<td>Gowin_PicoRV32_Top_inst/core/decoded_rd_1_s0/D</td>
<td>clk:[F]</td>
<td>clk:[R]</td>
<td>18.518</td>
<td>1.122</td>
<td>16.417</td>
</tr>
<tr>
<td>2</td>
<td>31.093</td>
<td>ahb_communicate_inst/addr_reg_13_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_19_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>37.037</td>
<td>0.451</td>
<td>5.459</td>
</tr>
<tr>
<td>3</td>
<td>31.114</td>
<td>ahb_communicate_inst/addr_reg_13_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_17_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>37.037</td>
<td>0.451</td>
<td>5.438</td>
</tr>
<tr>
<td>4</td>
<td>31.114</td>
<td>ahb_communicate_inst/addr_reg_13_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_18_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>37.037</td>
<td>0.451</td>
<td>5.438</td>
</tr>
<tr>
<td>5</td>
<td>31.114</td>
<td>ahb_communicate_inst/addr_reg_13_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_16_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>37.037</td>
<td>0.451</td>
<td>5.438</td>
</tr>
<tr>
<td>6</td>
<td>31.292</td>
<td>ahb_communicate_inst/addr_reg_13_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_2_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>37.037</td>
<td>0.179</td>
<td>5.531</td>
</tr>
<tr>
<td>7</td>
<td>31.374</td>
<td>ahb_communicate_inst/addr_reg_13_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_20_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>37.037</td>
<td>0.451</td>
<td>5.177</td>
</tr>
<tr>
<td>8</td>
<td>31.381</td>
<td>ahb_communicate_inst/addr_reg_13_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_8_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>37.037</td>
<td>0.179</td>
<td>5.441</td>
</tr>
<tr>
<td>9</td>
<td>31.462</td>
<td>ahb_communicate_inst/addr_reg_13_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_1_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>37.037</td>
<td>0.200</td>
<td>5.340</td>
</tr>
<tr>
<td>10</td>
<td>31.493</td>
<td>ahb_communicate_inst/addr_reg_13_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_0_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>37.037</td>
<td>0.296</td>
<td>5.213</td>
</tr>
<tr>
<td>11</td>
<td>31.493</td>
<td>ahb_communicate_inst/addr_reg_13_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_15_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>37.037</td>
<td>0.296</td>
<td>5.213</td>
</tr>
<tr>
<td>12</td>
<td>31.493</td>
<td>ahb_communicate_inst/addr_reg_13_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_14_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>37.037</td>
<td>0.296</td>
<td>5.213</td>
</tr>
<tr>
<td>13</td>
<td>31.493</td>
<td>ahb_communicate_inst/addr_reg_13_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_13_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>37.037</td>
<td>0.296</td>
<td>5.213</td>
</tr>
<tr>
<td>14</td>
<td>31.535</td>
<td>ahb_communicate_inst/addr_reg_13_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_7_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>37.037</td>
<td>0.179</td>
<td>5.288</td>
</tr>
<tr>
<td>15</td>
<td>31.659</td>
<td>ahb_communicate_inst/addr_reg_13_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_23_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>37.037</td>
<td>0.282</td>
<td>5.061</td>
</tr>
<tr>
<td>16</td>
<td>31.661</td>
<td>ahb_communicate_inst/addr_reg_13_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_4_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>37.037</td>
<td>0.200</td>
<td>5.141</td>
</tr>
<tr>
<td>17</td>
<td>31.725</td>
<td>ahb_communicate_inst/addr_reg_13_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_9_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>37.037</td>
<td>0.222</td>
<td>5.055</td>
</tr>
<tr>
<td>18</td>
<td>31.740</td>
<td>ahb_communicate_inst/addr_reg_13_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_5_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>37.037</td>
<td>0.222</td>
<td>5.040</td>
</tr>
<tr>
<td>19</td>
<td>31.741</td>
<td>ahb_communicate_inst/addr_reg_13_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_12_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>37.037</td>
<td>0.282</td>
<td>4.979</td>
</tr>
<tr>
<td>20</td>
<td>31.741</td>
<td>ahb_communicate_inst/addr_reg_13_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_10_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>37.037</td>
<td>0.282</td>
<td>4.979</td>
</tr>
<tr>
<td>21</td>
<td>31.741</td>
<td>ahb_communicate_inst/addr_reg_13_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_11_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>37.037</td>
<td>0.282</td>
<td>4.979</td>
</tr>
<tr>
<td>22</td>
<td>31.741</td>
<td>ahb_communicate_inst/addr_reg_13_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_22_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>37.037</td>
<td>0.282</td>
<td>4.979</td>
</tr>
<tr>
<td>23</td>
<td>31.741</td>
<td>ahb_communicate_inst/addr_reg_13_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_21_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>37.037</td>
<td>0.282</td>
<td>4.979</td>
</tr>
<tr>
<td>24</td>
<td>31.748</td>
<td>ahb_communicate_inst/addr_reg_13_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_6_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>37.037</td>
<td>0.050</td>
<td>5.204</td>
</tr>
<tr>
<td>25</td>
<td>31.748</td>
<td>ahb_communicate_inst/addr_reg_13_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_3_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>37.037</td>
<td>0.050</td>
<td>5.204</td>
</tr>
</table>
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
<h4>Report Command:report_timing -hold -from_clock [get_clocks {clk*}] -to_clock [get_clocks {clk*}] -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>0.044</td>
<td>Gowin_PicoRV32_Top_inst/wb/wbm_dat_o_15_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/wbuart_ins/uart_setup_15_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>-0.408</td>
<td>0.462</td>
</tr>
<tr>
<td>2</td>
<td>0.425</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_2_s0/Q</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_2_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.436</td>
</tr>
<tr>
<td>3</td>
<td>0.425</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_6_s0/Q</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_6_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.436</td>
</tr>
<tr>
<td>4</td>
<td>0.425</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_2_s0/Q</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_2_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.436</td>
</tr>
<tr>
<td>5</td>
<td>0.425</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_6_s0/Q</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_6_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.436</td>
</tr>
<tr>
<td>6</td>
<td>0.425</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_2_s0/Q</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_2_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.436</td>
</tr>
<tr>
<td>7</td>
<td>0.427</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_6_s0/Q</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_6_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.438</td>
</tr>
<tr>
<td>8</td>
<td>0.546</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_7_s0/Q</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_7_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.557</td>
</tr>
<tr>
<td>9</td>
<td>0.546</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_4_s0/Q</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_4_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.557</td>
</tr>
<tr>
<td>10</td>
<td>0.546</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_4_s0/Q</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_4_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.557</td>
</tr>
<tr>
<td>11</td>
<td>0.546</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_3_s0/Q</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_3_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.557</td>
</tr>
<tr>
<td>12</td>
<td>0.546</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_3_s0/Q</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_3_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.557</td>
</tr>
<tr>
<td>13</td>
<td>0.546</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_4_s0/Q</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_4_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.557</td>
</tr>
<tr>
<td>14</td>
<td>0.546</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_3_s0/Q</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_3_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.557</td>
</tr>
<tr>
<td>15</td>
<td>0.547</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_5_s0/Q</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_5_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.558</td>
</tr>
<tr>
<td>16</td>
<td>0.547</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_5_s0/Q</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_5_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.558</td>
</tr>
<tr>
<td>17</td>
<td>0.550</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_5_s0/Q</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_5_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.561</td>
</tr>
<tr>
<td>18</td>
<td>0.656</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_6_s0/Q</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_7_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.667</td>
</tr>
<tr>
<td>19</td>
<td>0.658</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_6_s0/Q</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_7_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.669</td>
</tr>
<tr>
<td>20</td>
<td>0.671</td>
<td>ahb_communicate_inst/addr_reg_2_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_3_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>-0.140</td>
<td>0.821</td>
</tr>
<tr>
<td>21</td>
<td>0.707</td>
<td>ahb_communicate_inst/addr_reg_2_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_0_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.016</td>
<td>0.702</td>
</tr>
<tr>
<td>22</td>
<td>0.806</td>
<td>ahb_communicate_inst/addr_reg_2_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_6_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>-0.140</td>
<td>0.957</td>
</tr>
<tr>
<td>23</td>
<td>0.821</td>
<td>ahb_communicate_inst/addr_reg_2_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_2_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>-0.024</td>
<td>0.856</td>
</tr>
<tr>
<td>24</td>
<td>0.821</td>
<td>ahb_communicate_inst/addr_reg_2_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_8_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>-0.024</td>
<td>0.856</td>
</tr>
<tr>
<td>25</td>
<td>0.825</td>
<td>ahb_communicate_inst/addr_reg_2_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_5_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.012</td>
<td>0.824</td>
</tr>
</table>
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr style="color: #FF0000;">
<td>1</td>
<td>-2.611</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
<td>Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_8_s0/CLEAR</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>0.123</td>
<td>-0.208</td>
<td>2.872</td>
</tr>
<tr style="color: #FF0000;">
<td>2</td>
<td>-2.611</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
<td>Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_11_s0/CLEAR</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>0.123</td>
<td>-0.208</td>
<td>2.872</td>
</tr>
<tr style="color: #FF0000;">
<td>3</td>
<td>-2.542</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RESET</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>0.001</td>
<td>0.208</td>
<td>1.802</td>
</tr>
<tr style="color: #FF0000;">
<td>4</td>
<td>-2.542</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RESET</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>0.001</td>
<td>0.208</td>
<td>1.802</td>
</tr>
<tr style="color: #FF0000;">
<td>5</td>
<td>-2.376</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
<td>Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_9_s0/CLEAR</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>0.123</td>
<td>-0.208</td>
<td>2.637</td>
</tr>
<tr style="color: #FF0000;">
<td>6</td>
<td>-2.376</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
<td>Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_10_s0/CLEAR</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>0.123</td>
<td>-0.208</td>
<td>2.637</td>
</tr>
<tr style="color: #FF0000;">
<td>7</td>
<td>-2.376</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
<td>Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_25_s0/CLEAR</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>0.123</td>
<td>-0.208</td>
<td>2.637</td>
</tr>
<tr style="color: #FF0000;">
<td>8</td>
<td>-2.197</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/u_ck_gen/RESET</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>0.001</td>
<td>0.208</td>
<td>1.802</td>
</tr>
<tr style="color: #FF0000;">
<td>9</td>
<td>-2.197</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/RESET</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>0.001</td>
<td>0.208</td>
<td>1.802</td>
</tr>
<tr style="color: #FF0000;">
<td>10</td>
<td>-2.197</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/RESET</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>0.001</td>
<td>0.208</td>
<td>1.802</td>
</tr>
<tr style="color: #FF0000;">
<td>11</td>
<td>-2.197</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/RESET</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>0.001</td>
<td>0.208</td>
<td>1.802</td>
</tr>
<tr style="color: #FF0000;">
<td>12</td>
<td>-2.197</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/RESET</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>0.001</td>
<td>0.208</td>
<td>1.802</td>
</tr>
<tr style="color: #FF0000;">
<td>13</td>
<td>-2.197</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/RESET</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>0.001</td>
<td>0.208</td>
<td>1.802</td>
</tr>
<tr style="color: #FF0000;">
<td>14</td>
<td>-2.197</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen/RESET</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>0.001</td>
<td>0.208</td>
<td>1.802</td>
</tr>
<tr style="color: #FF0000;">
<td>15</td>
<td>-2.197</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[16].u_cmd_gen/RESET</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>0.001</td>
<td>0.208</td>
<td>1.802</td>
</tr>
<tr style="color: #FF0000;">
<td>16</td>
<td>-2.197</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[15].u_cmd_gen/RESET</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>0.001</td>
<td>0.208</td>
<td>1.802</td>
</tr>
<tr style="color: #FF0000;">
<td>17</td>
<td>-2.197</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[14].u_cmd_gen/RESET</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>0.001</td>
<td>0.208</td>
<td>1.802</td>
</tr>
<tr style="color: #FF0000;">
<td>18</td>
<td>-2.197</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[13].u_cmd_gen/RESET</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>0.001</td>
<td>0.208</td>
<td>1.802</td>
</tr>
<tr style="color: #FF0000;">
<td>19</td>
<td>-2.197</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[12].u_cmd_gen/RESET</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>0.001</td>
<td>0.208</td>
<td>1.802</td>
</tr>
<tr style="color: #FF0000;">
<td>20</td>
<td>-2.197</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[11].u_cmd_gen/RESET</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>0.001</td>
<td>0.208</td>
<td>1.802</td>
</tr>
<tr style="color: #FF0000;">
<td>21</td>
<td>-2.197</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[10].u_cmd_gen/RESET</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>0.001</td>
<td>0.208</td>
<td>1.802</td>
</tr>
<tr style="color: #FF0000;">
<td>22</td>
<td>-2.197</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen/RESET</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>0.001</td>
<td>0.208</td>
<td>1.802</td>
</tr>
<tr style="color: #FF0000;">
<td>23</td>
<td>-2.197</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[8].u_cmd_gen/RESET</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>0.001</td>
<td>0.208</td>
<td>1.802</td>
</tr>
<tr style="color: #FF0000;">
<td>24</td>
<td>-2.197</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[7].u_cmd_gen/RESET</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>0.001</td>
<td>0.208</td>
<td>1.802</td>
</tr>
<tr style="color: #FF0000;">
<td>25</td>
<td>-2.197</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[6].u_cmd_gen/RESET</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>0.001</td>
<td>0.208</td>
<td>1.802</td>
</tr>
</table>
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>0.484</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[3].ram_dfflr/qout_r_5_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.018</td>
<td>0.477</td>
</tr>
<tr>
<td>2</td>
<td>0.484</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[3].ram_dfflr/qout_r_28_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.018</td>
<td>0.477</td>
</tr>
<tr>
<td>3</td>
<td>0.484</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[1].ram_dfflr/qout_r_1_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.018</td>
<td>0.477</td>
</tr>
<tr>
<td>4</td>
<td>0.484</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[1].ram_dfflr/qout_r_2_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.018</td>
<td>0.477</td>
</tr>
<tr>
<td>5</td>
<td>0.508</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[6].ram_dfflr/qout_r_6_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.041</td>
<td>0.477</td>
</tr>
<tr>
<td>6</td>
<td>0.508</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[6].ram_dfflr/qout_r_13_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.041</td>
<td>0.477</td>
</tr>
<tr>
<td>7</td>
<td>0.508</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[4].ram_dfflr/qout_r_1_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.041</td>
<td>0.477</td>
</tr>
<tr>
<td>8</td>
<td>0.508</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[4].ram_dfflr/qout_r_6_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.041</td>
<td>0.477</td>
</tr>
<tr>
<td>9</td>
<td>0.600</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
<td>Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/read_dog_cnt_4_s0/CLEAR</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.611</td>
</tr>
<tr>
<td>10</td>
<td>0.652</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/u_i_vld_sync/sync_gen[1].i_is_not_0.sync_dffr/qout_r_0_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>-0.149</td>
<td>0.813</td>
</tr>
<tr>
<td>11</td>
<td>0.652</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/u_i_vld_sync/sync_gen[0].i_is_0.sync_dffr/qout_r_0_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>-0.149</td>
<td>0.813</td>
</tr>
<tr>
<td>12</td>
<td>0.670</td>
<td>xcorr1/finished_temp1_s0/Q</td>
<td>xcorr3/mul_add_result_6_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>-0.145</td>
<td>0.826</td>
</tr>
<tr>
<td>13</td>
<td>0.670</td>
<td>xcorr1/finished_temp1_s0/Q</td>
<td>xcorr3/mul_add_result_9_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>-0.145</td>
<td>0.826</td>
</tr>
<tr>
<td>14</td>
<td>0.670</td>
<td>xcorr1/finished_temp1_s0/Q</td>
<td>xcorr3/mul_add_max_7_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>-0.145</td>
<td>0.826</td>
</tr>
<tr>
<td>15</td>
<td>0.670</td>
<td>xcorr1/finished_temp1_s0/Q</td>
<td>xcorr3/mul_add_max_8_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>-0.145</td>
<td>0.826</td>
</tr>
<tr>
<td>16</td>
<td>0.670</td>
<td>xcorr1/finished_temp1_s0/Q</td>
<td>xcorr3/mul_add_max_9_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>-0.145</td>
<td>0.826</td>
</tr>
<tr>
<td>17</td>
<td>0.670</td>
<td>xcorr1/finished_temp1_s0/Q</td>
<td>xcorr3/mul_add_max_11_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>-0.145</td>
<td>0.826</td>
</tr>
<tr>
<td>18</td>
<td>0.676</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_3_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>-0.131</td>
<td>0.818</td>
</tr>
<tr>
<td>19</td>
<td>0.676</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_8_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>-0.131</td>
<td>0.818</td>
</tr>
<tr>
<td>20</td>
<td>0.676</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_9_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>-0.131</td>
<td>0.818</td>
</tr>
<tr>
<td>21</td>
<td>0.676</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_10_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>-0.131</td>
<td>0.818</td>
</tr>
<tr>
<td>22</td>
<td>0.682</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_12_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>-0.125</td>
<td>0.818</td>
</tr>
<tr>
<td>23</td>
<td>0.682</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_15_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>-0.125</td>
<td>0.818</td>
</tr>
<tr>
<td>24</td>
<td>0.682</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_20_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>-0.125</td>
<td>0.818</td>
</tr>
<tr>
<td>25</td>
<td>0.682</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_32_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>-0.125</td>
<td>0.818</td>
</tr>
</table>
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Number</th>
<th class="label">Slack</th>
<th class="label">Actual Width</th>
<th class="label">Required Width</th>
<th class="label">Type</th>
<th class="label">Clock</th>
<th class="label">Objects</th>
</tr>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<tr>
<td>1</td>
<td>3.190</td>
<td>4.190</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_23_s0</td>
</tr>
<tr>
<td>2</td>
<td>3.190</td>
<td>4.190</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_22_s0</td>
</tr>
<tr>
<td>3</td>
<td>3.190</td>
<td>4.190</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_21_s0</td>
</tr>
<tr>
<td>4</td>
<td>3.190</td>
<td>4.190</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_20_s0</td>
</tr>
<tr>
<td>5</td>
<td>3.190</td>
<td>4.190</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_19_s0</td>
</tr>
<tr>
<td>6</td>
<td>3.190</td>
<td>4.190</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_18_s0</td>
</tr>
<tr>
<td>7</td>
<td>3.190</td>
<td>4.190</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_17_s0</td>
</tr>
<tr>
<td>8</td>
<td>3.190</td>
<td>4.190</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_16_s0</td>
</tr>
<tr>
<td>9</td>
<td>3.190</td>
<td>4.190</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_14_s0</td>
</tr>
<tr>
<td>10</td>
<td>3.190</td>
<td>4.190</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_6_s0</td>
</tr>
</table>
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
<h4>Report Command:report_timing -setup -from_clock [get_clocks {clk*}] -to_clock [get_clocks {clk*}] -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.944</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>37.768</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>38.712</td>
</tr>
<tr>
<td class="label">From</td>
<td>Gowin_PicoRV32_Top_inst/rstdly_15_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/core/decoded_rd_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>18.518</td>
<td>18.518</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>19.206</td>
<td>0.688</td>
<td>tINS</td>
<td>FF</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>21.350</td>
<td>2.144</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C45[2][B]</td>
<td>Gowin_PicoRV32_Top_inst/rstdly_15_s1/CLK</td>
</tr>
<tr>
<td>21.582</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>26</td>
<td>R22C45[2][B]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/rstdly_15_s1/Q</td>
</tr>
<tr>
<td>22.605</td>
<td>1.023</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C30[0][A]</td>
<td>Gowin_PicoRV32_Top_inst/core/n7354_s1/I3</td>
</tr>
<tr>
<td>22.976</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R14C30[0][A]</td>
<td style=" background: #97FFFF;">Gowin_PicoRV32_Top_inst/core/n7354_s1/F</td>
</tr>
<tr>
<td>23.481</td>
<td>0.504</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C31[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/core/mem_rdata_latched_12_s5/I3</td>
</tr>
<tr>
<td>23.852</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>21</td>
<td>R13C31[1][A]</td>
<td style=" background: #97FFFF;">Gowin_PicoRV32_Top_inst/core/mem_rdata_latched_12_s5/F</td>
</tr>
<tr>
<td>25.266</td>
<td>1.414</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C32[3][A]</td>
<td>Gowin_PicoRV32_Top_inst/core/mem_rdata_latched_4_s6/I0</td>
</tr>
<tr>
<td>25.821</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R14C32[3][A]</td>
<td style=" background: #97FFFF;">Gowin_PicoRV32_Top_inst/core/mem_rdata_latched_4_s6/F</td>
</tr>
<tr>
<td>27.233</td>
<td>1.412</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C35[0][B]</td>
<td>Gowin_PicoRV32_Top_inst/core/mem_rdata_latched_4_s3/I3</td>
</tr>
<tr>
<td>27.686</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R14C35[0][B]</td>
<td style=" background: #97FFFF;">Gowin_PicoRV32_Top_inst/core/mem_rdata_latched_4_s3/F</td>
</tr>
<tr>
<td>28.091</td>
<td>0.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C35[2][A]</td>
<td>Gowin_PicoRV32_Top_inst/core/n5376_s3/I3</td>
</tr>
<tr>
<td>28.544</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C35[2][A]</td>
<td style=" background: #97FFFF;">Gowin_PicoRV32_Top_inst/core/n5376_s3/F</td>
</tr>
<tr>
<td>30.426</td>
<td>1.881</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C35[0][B]</td>
<td>Gowin_PicoRV32_Top_inst/core/n5376_s2/I2</td>
</tr>
<tr>
<td>30.981</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R17C35[0][B]</td>
<td style=" background: #97FFFF;">Gowin_PicoRV32_Top_inst/core/n5376_s2/F</td>
</tr>
<tr>
<td>31.523</td>
<td>0.543</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C34[3][B]</td>
<td>Gowin_PicoRV32_Top_inst/core/n5772_s4/I2</td>
</tr>
<tr>
<td>32.078</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R13C34[3][B]</td>
<td style=" background: #97FFFF;">Gowin_PicoRV32_Top_inst/core/n5772_s4/F</td>
</tr>
<tr>
<td>34.091</td>
<td>2.013</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C27[2][A]</td>
<td>Gowin_PicoRV32_Top_inst/core/n5708_s3/I0</td>
</tr>
<tr>
<td>34.544</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R15C27[2][A]</td>
<td style=" background: #97FFFF;">Gowin_PicoRV32_Top_inst/core/n5708_s3/F</td>
</tr>
<tr>
<td>35.730</td>
<td>1.186</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C27[3][A]</td>
<td>Gowin_PicoRV32_Top_inst/core/n5708_s1/I2</td>
</tr>
<tr>
<td>36.183</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R14C27[3][A]</td>
<td style=" background: #97FFFF;">Gowin_PicoRV32_Top_inst/core/n5708_s1/F</td>
</tr>
<tr>
<td>37.219</td>
<td>1.036</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C35[0][A]</td>
<td>Gowin_PicoRV32_Top_inst/core/n5709_s0/I1</td>
</tr>
<tr>
<td>37.768</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R14C35[0][A]</td>
<td style=" background: #97FFFF;">Gowin_PicoRV32_Top_inst/core/n5709_s0/F</td>
</tr>
<tr>
<td>37.768</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C35[0][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/core/decoded_rd_1_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>37.719</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>38.747</td>
<td>1.028</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C35[0][A]</td>
<td>Gowin_PicoRV32_Top_inst/core/decoded_rd_1_s0/CLK</td>
</tr>
<tr>
<td>38.712</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R14C35[0][A]</td>
<td>Gowin_PicoRV32_Top_inst/core/decoded_rd_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.122</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>18.518</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>11</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.688, 24.277%; route: 2.144, 75.723%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.768, 29.042%; route: 11.417, 69.545%; tC2Q: 0.232, 1.413%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 39.906%; route: 1.028, 60.094%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>31.093</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.646</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>38.739</td>
</tr>
<tr>
<td class="label">From</td>
<td>ahb_communicate_inst/addr_reg_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_19_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.188</td>
<td>1.505</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td>ahb_communicate_inst/addr_reg_13_s0/CLK</td>
</tr>
<tr>
<td>2.420</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td style=" font-weight:bold;">ahb_communicate_inst/addr_reg_13_s0/Q</td>
</tr>
<tr>
<td>3.374</td>
<td>0.954</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td>ahb_communicate_inst/n335_s5/I1</td>
</tr>
<tr>
<td>3.929</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s5/F</td>
</tr>
<tr>
<td>4.176</td>
<td>0.247</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td>ahb_communicate_inst/n335_s4/I3</td>
</tr>
<tr>
<td>4.638</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s4/F</td>
</tr>
<tr>
<td>4.810</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C30[2][B]</td>
<td>ahb_communicate_inst/n335_s2/I3</td>
</tr>
<tr>
<td>5.263</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R26C30[2][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s2/F</td>
</tr>
<tr>
<td>5.682</td>
<td>0.419</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[0][A]</td>
<td>ahb_communicate_inst/hrdata_i_9_s1/I3</td>
</tr>
<tr>
<td>6.237</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R26C31[0][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_9_s1/F</td>
</tr>
<tr>
<td>7.076</td>
<td>0.839</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C28[0][B]</td>
<td>ahb_communicate_inst/hrdata_19_s6/I2</td>
</tr>
<tr>
<td>7.646</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C28[0][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_19_s6/F</td>
</tr>
<tr>
<td>7.646</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[0][B]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_19_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>37.719</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>38.774</td>
<td>1.055</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[0][B]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_19_s0/CLK</td>
</tr>
<tr>
<td>38.739</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R26C28[0][B]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_19_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.451</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>37.037</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 31.196%; route: 1.505, 68.804%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.595, 47.538%; route: 2.632, 48.212%; tC2Q: 0.232, 4.250%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 39.286%; route: 1.055, 60.714%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>31.114</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.625</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>38.739</td>
</tr>
<tr>
<td class="label">From</td>
<td>ahb_communicate_inst/addr_reg_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_17_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.188</td>
<td>1.505</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td>ahb_communicate_inst/addr_reg_13_s0/CLK</td>
</tr>
<tr>
<td>2.420</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td style=" font-weight:bold;">ahb_communicate_inst/addr_reg_13_s0/Q</td>
</tr>
<tr>
<td>3.374</td>
<td>0.954</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td>ahb_communicate_inst/n335_s5/I1</td>
</tr>
<tr>
<td>3.929</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s5/F</td>
</tr>
<tr>
<td>4.176</td>
<td>0.247</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td>ahb_communicate_inst/n335_s4/I3</td>
</tr>
<tr>
<td>4.638</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s4/F</td>
</tr>
<tr>
<td>4.810</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C30[2][B]</td>
<td>ahb_communicate_inst/n335_s2/I3</td>
</tr>
<tr>
<td>5.263</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R26C30[2][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s2/F</td>
</tr>
<tr>
<td>5.682</td>
<td>0.419</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[0][A]</td>
<td>ahb_communicate_inst/hrdata_i_9_s1/I3</td>
</tr>
<tr>
<td>6.237</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R26C31[0][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_9_s1/F</td>
</tr>
<tr>
<td>7.076</td>
<td>0.839</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C28[1][B]</td>
<td>ahb_communicate_inst/hrdata_17_s6/I2</td>
</tr>
<tr>
<td>7.625</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C28[1][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_17_s6/F</td>
</tr>
<tr>
<td>7.625</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[1][B]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_17_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>37.719</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>38.774</td>
<td>1.055</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[1][B]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_17_s0/CLK</td>
</tr>
<tr>
<td>38.739</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R26C28[1][B]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_17_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.451</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>37.037</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 31.196%; route: 1.505, 68.804%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.574, 47.336%; route: 2.632, 48.398%; tC2Q: 0.232, 4.266%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 39.286%; route: 1.055, 60.714%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>31.114</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.625</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>38.739</td>
</tr>
<tr>
<td class="label">From</td>
<td>ahb_communicate_inst/addr_reg_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_18_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.188</td>
<td>1.505</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td>ahb_communicate_inst/addr_reg_13_s0/CLK</td>
</tr>
<tr>
<td>2.420</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td style=" font-weight:bold;">ahb_communicate_inst/addr_reg_13_s0/Q</td>
</tr>
<tr>
<td>3.374</td>
<td>0.954</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td>ahb_communicate_inst/n335_s5/I1</td>
</tr>
<tr>
<td>3.929</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s5/F</td>
</tr>
<tr>
<td>4.176</td>
<td>0.247</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td>ahb_communicate_inst/n335_s4/I3</td>
</tr>
<tr>
<td>4.638</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s4/F</td>
</tr>
<tr>
<td>4.810</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C30[2][B]</td>
<td>ahb_communicate_inst/n335_s2/I3</td>
</tr>
<tr>
<td>5.263</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R26C30[2][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s2/F</td>
</tr>
<tr>
<td>5.682</td>
<td>0.419</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[0][A]</td>
<td>ahb_communicate_inst/hrdata_i_9_s1/I3</td>
</tr>
<tr>
<td>6.237</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R26C31[0][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_9_s1/F</td>
</tr>
<tr>
<td>7.076</td>
<td>0.839</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C28[1][A]</td>
<td>ahb_communicate_inst/hrdata_18_s6/I2</td>
</tr>
<tr>
<td>7.625</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C28[1][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_18_s6/F</td>
</tr>
<tr>
<td>7.625</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[1][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_18_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>37.719</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>38.774</td>
<td>1.055</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_18_s0/CLK</td>
</tr>
<tr>
<td>38.739</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R26C28[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_18_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.451</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>37.037</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 31.196%; route: 1.505, 68.804%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.574, 47.336%; route: 2.632, 48.398%; tC2Q: 0.232, 4.266%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 39.286%; route: 1.055, 60.714%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>31.114</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.625</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>38.739</td>
</tr>
<tr>
<td class="label">From</td>
<td>ahb_communicate_inst/addr_reg_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_16_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.188</td>
<td>1.505</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td>ahb_communicate_inst/addr_reg_13_s0/CLK</td>
</tr>
<tr>
<td>2.420</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td style=" font-weight:bold;">ahb_communicate_inst/addr_reg_13_s0/Q</td>
</tr>
<tr>
<td>3.374</td>
<td>0.954</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td>ahb_communicate_inst/n335_s5/I1</td>
</tr>
<tr>
<td>3.929</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s5/F</td>
</tr>
<tr>
<td>4.176</td>
<td>0.247</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td>ahb_communicate_inst/n335_s4/I3</td>
</tr>
<tr>
<td>4.638</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s4/F</td>
</tr>
<tr>
<td>4.810</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C30[2][B]</td>
<td>ahb_communicate_inst/n335_s2/I3</td>
</tr>
<tr>
<td>5.263</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R26C30[2][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s2/F</td>
</tr>
<tr>
<td>5.682</td>
<td>0.419</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[0][A]</td>
<td>ahb_communicate_inst/hrdata_i_9_s1/I3</td>
</tr>
<tr>
<td>6.237</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R26C31[0][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_9_s1/F</td>
</tr>
<tr>
<td>7.076</td>
<td>0.839</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C28[2][A]</td>
<td>ahb_communicate_inst/hrdata_16_s6/I2</td>
</tr>
<tr>
<td>7.625</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C28[2][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_16_s6/F</td>
</tr>
<tr>
<td>7.625</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[2][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_16_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>37.719</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>38.774</td>
<td>1.055</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[2][A]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_16_s0/CLK</td>
</tr>
<tr>
<td>38.739</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R26C28[2][A]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_16_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.451</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>37.037</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 31.196%; route: 1.505, 68.804%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.574, 47.336%; route: 2.632, 48.398%; tC2Q: 0.232, 4.266%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 39.286%; route: 1.055, 60.714%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>31.292</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.719</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>39.010</td>
</tr>
<tr>
<td class="label">From</td>
<td>ahb_communicate_inst/addr_reg_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.188</td>
<td>1.505</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td>ahb_communicate_inst/addr_reg_13_s0/CLK</td>
</tr>
<tr>
<td>2.420</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td style=" font-weight:bold;">ahb_communicate_inst/addr_reg_13_s0/Q</td>
</tr>
<tr>
<td>3.374</td>
<td>0.954</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td>ahb_communicate_inst/n335_s5/I1</td>
</tr>
<tr>
<td>3.929</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s5/F</td>
</tr>
<tr>
<td>4.176</td>
<td>0.247</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td>ahb_communicate_inst/n335_s4/I3</td>
</tr>
<tr>
<td>4.638</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s4/F</td>
</tr>
<tr>
<td>4.810</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C30[2][B]</td>
<td>ahb_communicate_inst/n335_s2/I3</td>
</tr>
<tr>
<td>5.263</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R26C30[2][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s2/F</td>
</tr>
<tr>
<td>5.682</td>
<td>0.419</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[0][A]</td>
<td>ahb_communicate_inst/hrdata_i_9_s1/I3</td>
</tr>
<tr>
<td>6.237</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R26C31[0][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_9_s1/F</td>
</tr>
<tr>
<td>7.170</td>
<td>0.933</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C34[0][B]</td>
<td>ahb_communicate_inst/hrdata_i_2_s/I3</td>
</tr>
<tr>
<td>7.719</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R29C34[0][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_2_s/F</td>
</tr>
<tr>
<td>7.719</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C34[0][B]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>37.719</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>39.045</td>
<td>1.326</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C34[0][B]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_2_s0/CLK</td>
</tr>
<tr>
<td>39.010</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C34[0][B]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.179</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>37.037</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 31.196%; route: 1.505, 68.804%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.574, 46.539%; route: 2.725, 49.267%; tC2Q: 0.232, 4.195%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 33.982%; route: 1.326, 66.018%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>31.374</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.365</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>38.739</td>
</tr>
<tr>
<td class="label">From</td>
<td>ahb_communicate_inst/addr_reg_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_20_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.188</td>
<td>1.505</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td>ahb_communicate_inst/addr_reg_13_s0/CLK</td>
</tr>
<tr>
<td>2.420</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td style=" font-weight:bold;">ahb_communicate_inst/addr_reg_13_s0/Q</td>
</tr>
<tr>
<td>3.374</td>
<td>0.954</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td>ahb_communicate_inst/n335_s5/I1</td>
</tr>
<tr>
<td>3.929</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s5/F</td>
</tr>
<tr>
<td>4.176</td>
<td>0.247</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td>ahb_communicate_inst/n335_s4/I3</td>
</tr>
<tr>
<td>4.638</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s4/F</td>
</tr>
<tr>
<td>4.810</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C30[2][B]</td>
<td>ahb_communicate_inst/n335_s2/I3</td>
</tr>
<tr>
<td>5.263</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R26C30[2][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s2/F</td>
</tr>
<tr>
<td>5.682</td>
<td>0.419</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[0][A]</td>
<td>ahb_communicate_inst/hrdata_i_9_s1/I3</td>
</tr>
<tr>
<td>6.237</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R26C31[0][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_9_s1/F</td>
</tr>
<tr>
<td>6.903</td>
<td>0.666</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C28[0][A]</td>
<td>ahb_communicate_inst/hrdata_20_s6/I2</td>
</tr>
<tr>
<td>7.365</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C28[0][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_20_s6/F</td>
</tr>
<tr>
<td>7.365</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[0][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_20_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>37.719</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>38.774</td>
<td>1.055</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[0][A]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_20_s0/CLK</td>
</tr>
<tr>
<td>38.739</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R26C28[0][A]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_20_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.451</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>37.037</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 31.196%; route: 1.505, 68.804%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.487, 48.036%; route: 2.458, 47.483%; tC2Q: 0.232, 4.481%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 39.286%; route: 1.055, 60.714%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>31.381</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.629</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>39.010</td>
</tr>
<tr>
<td class="label">From</td>
<td>ahb_communicate_inst/addr_reg_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.188</td>
<td>1.505</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td>ahb_communicate_inst/addr_reg_13_s0/CLK</td>
</tr>
<tr>
<td>2.420</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td style=" font-weight:bold;">ahb_communicate_inst/addr_reg_13_s0/Q</td>
</tr>
<tr>
<td>3.374</td>
<td>0.954</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td>ahb_communicate_inst/n335_s5/I1</td>
</tr>
<tr>
<td>3.929</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s5/F</td>
</tr>
<tr>
<td>4.176</td>
<td>0.247</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td>ahb_communicate_inst/n335_s4/I3</td>
</tr>
<tr>
<td>4.638</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s4/F</td>
</tr>
<tr>
<td>4.810</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C30[2][B]</td>
<td>ahb_communicate_inst/n335_s2/I3</td>
</tr>
<tr>
<td>5.263</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R26C30[2][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s2/F</td>
</tr>
<tr>
<td>5.682</td>
<td>0.419</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[0][A]</td>
<td>ahb_communicate_inst/hrdata_i_9_s1/I3</td>
</tr>
<tr>
<td>6.237</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R26C31[0][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_9_s1/F</td>
</tr>
<tr>
<td>7.167</td>
<td>0.930</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C34[0][A]</td>
<td>ahb_communicate_inst/hrdata_i_8_s/I3</td>
</tr>
<tr>
<td>7.629</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R29C34[0][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_8_s/F</td>
</tr>
<tr>
<td>7.629</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C34[0][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_8_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>37.719</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>39.045</td>
<td>1.326</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C34[0][A]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_8_s0/CLK</td>
</tr>
<tr>
<td>39.010</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C34[0][A]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_8_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.179</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>37.037</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 31.196%; route: 1.505, 68.804%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.487, 45.704%; route: 2.722, 50.032%; tC2Q: 0.232, 4.264%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 33.982%; route: 1.326, 66.018%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>31.462</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.528</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>38.989</td>
</tr>
<tr>
<td class="label">From</td>
<td>ahb_communicate_inst/addr_reg_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.188</td>
<td>1.505</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td>ahb_communicate_inst/addr_reg_13_s0/CLK</td>
</tr>
<tr>
<td>2.420</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td style=" font-weight:bold;">ahb_communicate_inst/addr_reg_13_s0/Q</td>
</tr>
<tr>
<td>3.374</td>
<td>0.954</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td>ahb_communicate_inst/n335_s5/I1</td>
</tr>
<tr>
<td>3.929</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s5/F</td>
</tr>
<tr>
<td>4.176</td>
<td>0.247</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td>ahb_communicate_inst/n335_s4/I3</td>
</tr>
<tr>
<td>4.638</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s4/F</td>
</tr>
<tr>
<td>4.810</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C30[2][B]</td>
<td>ahb_communicate_inst/n335_s2/I3</td>
</tr>
<tr>
<td>5.263</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R26C30[2][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s2/F</td>
</tr>
<tr>
<td>5.682</td>
<td>0.419</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[0][A]</td>
<td>ahb_communicate_inst/hrdata_i_9_s1/I3</td>
</tr>
<tr>
<td>6.237</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R26C31[0][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_9_s1/F</td>
</tr>
<tr>
<td>6.958</td>
<td>0.720</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C35[0][A]</td>
<td>ahb_communicate_inst/hrdata_i_1_s/I3</td>
</tr>
<tr>
<td>7.528</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R29C35[0][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_1_s/F</td>
</tr>
<tr>
<td>7.528</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C35[0][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_1_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>37.719</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>39.024</td>
<td>1.305</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C35[0][A]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_1_s0/CLK</td>
</tr>
<tr>
<td>38.989</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C35[0][A]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.200</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>37.037</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 31.196%; route: 1.505, 68.804%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.595, 48.597%; route: 2.513, 47.058%; tC2Q: 0.232, 4.345%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 34.342%; route: 1.305, 65.658%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>31.493</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.400</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>38.893</td>
</tr>
<tr>
<td class="label">From</td>
<td>ahb_communicate_inst/addr_reg_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.188</td>
<td>1.505</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td>ahb_communicate_inst/addr_reg_13_s0/CLK</td>
</tr>
<tr>
<td>2.420</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td style=" font-weight:bold;">ahb_communicate_inst/addr_reg_13_s0/Q</td>
</tr>
<tr>
<td>3.374</td>
<td>0.954</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td>ahb_communicate_inst/n335_s5/I1</td>
</tr>
<tr>
<td>3.929</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s5/F</td>
</tr>
<tr>
<td>4.176</td>
<td>0.247</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td>ahb_communicate_inst/n335_s4/I3</td>
</tr>
<tr>
<td>4.638</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s4/F</td>
</tr>
<tr>
<td>4.810</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C30[2][B]</td>
<td>ahb_communicate_inst/n335_s2/I3</td>
</tr>
<tr>
<td>5.263</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R26C30[2][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s2/F</td>
</tr>
<tr>
<td>5.682</td>
<td>0.419</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[0][A]</td>
<td>ahb_communicate_inst/hrdata_i_9_s1/I3</td>
</tr>
<tr>
<td>6.237</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R26C31[0][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_9_s1/F</td>
</tr>
<tr>
<td>6.938</td>
<td>0.701</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C28[1][A]</td>
<td>ahb_communicate_inst/hrdata_i_0_s/I3</td>
</tr>
<tr>
<td>7.400</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R27C28[1][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_0_s/F</td>
</tr>
<tr>
<td>7.400</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[1][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_0_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>37.719</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>38.928</td>
<td>1.209</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_0_s0/CLK</td>
</tr>
<tr>
<td>38.893</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R27C28[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.296</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>37.037</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 31.196%; route: 1.505, 68.804%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.487, 47.711%; route: 2.494, 47.838%; tC2Q: 0.232, 4.451%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 36.085%; route: 1.209, 63.915%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>31.493</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.400</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>38.893</td>
</tr>
<tr>
<td class="label">From</td>
<td>ahb_communicate_inst/addr_reg_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_15_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.188</td>
<td>1.505</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td>ahb_communicate_inst/addr_reg_13_s0/CLK</td>
</tr>
<tr>
<td>2.420</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td style=" font-weight:bold;">ahb_communicate_inst/addr_reg_13_s0/Q</td>
</tr>
<tr>
<td>3.374</td>
<td>0.954</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td>ahb_communicate_inst/n335_s5/I1</td>
</tr>
<tr>
<td>3.929</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s5/F</td>
</tr>
<tr>
<td>4.176</td>
<td>0.247</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td>ahb_communicate_inst/n335_s4/I3</td>
</tr>
<tr>
<td>4.638</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s4/F</td>
</tr>
<tr>
<td>4.810</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C30[2][B]</td>
<td>ahb_communicate_inst/n335_s2/I3</td>
</tr>
<tr>
<td>5.263</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R26C30[2][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s2/F</td>
</tr>
<tr>
<td>5.682</td>
<td>0.419</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[0][A]</td>
<td>ahb_communicate_inst/hrdata_i_9_s1/I3</td>
</tr>
<tr>
<td>6.237</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R26C31[0][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_9_s1/F</td>
</tr>
<tr>
<td>6.938</td>
<td>0.701</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C28[1][B]</td>
<td>ahb_communicate_inst/hrdata_15_s6/I2</td>
</tr>
<tr>
<td>7.400</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R27C28[1][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_15_s6/F</td>
</tr>
<tr>
<td>7.400</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[1][B]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_15_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>37.719</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>38.928</td>
<td>1.209</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[1][B]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_15_s0/CLK</td>
</tr>
<tr>
<td>38.893</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R27C28[1][B]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_15_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.296</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>37.037</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 31.196%; route: 1.505, 68.804%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.487, 47.711%; route: 2.494, 47.838%; tC2Q: 0.232, 4.451%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 36.085%; route: 1.209, 63.915%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>31.493</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.400</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>38.893</td>
</tr>
<tr>
<td class="label">From</td>
<td>ahb_communicate_inst/addr_reg_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_14_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.188</td>
<td>1.505</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td>ahb_communicate_inst/addr_reg_13_s0/CLK</td>
</tr>
<tr>
<td>2.420</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td style=" font-weight:bold;">ahb_communicate_inst/addr_reg_13_s0/Q</td>
</tr>
<tr>
<td>3.374</td>
<td>0.954</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td>ahb_communicate_inst/n335_s5/I1</td>
</tr>
<tr>
<td>3.929</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s5/F</td>
</tr>
<tr>
<td>4.176</td>
<td>0.247</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td>ahb_communicate_inst/n335_s4/I3</td>
</tr>
<tr>
<td>4.638</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s4/F</td>
</tr>
<tr>
<td>4.810</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C30[2][B]</td>
<td>ahb_communicate_inst/n335_s2/I3</td>
</tr>
<tr>
<td>5.263</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R26C30[2][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s2/F</td>
</tr>
<tr>
<td>5.682</td>
<td>0.419</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[0][A]</td>
<td>ahb_communicate_inst/hrdata_i_9_s1/I3</td>
</tr>
<tr>
<td>6.237</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R26C31[0][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_9_s1/F</td>
</tr>
<tr>
<td>6.938</td>
<td>0.701</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C28[2][A]</td>
<td>ahb_communicate_inst/hrdata_14_s6/I2</td>
</tr>
<tr>
<td>7.400</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R27C28[2][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_14_s6/F</td>
</tr>
<tr>
<td>7.400</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[2][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_14_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>37.719</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>38.928</td>
<td>1.209</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[2][A]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_14_s0/CLK</td>
</tr>
<tr>
<td>38.893</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R27C28[2][A]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_14_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.296</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>37.037</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 31.196%; route: 1.505, 68.804%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.487, 47.711%; route: 2.494, 47.838%; tC2Q: 0.232, 4.451%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 36.085%; route: 1.209, 63.915%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>31.493</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.400</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>38.893</td>
</tr>
<tr>
<td class="label">From</td>
<td>ahb_communicate_inst/addr_reg_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_13_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.188</td>
<td>1.505</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td>ahb_communicate_inst/addr_reg_13_s0/CLK</td>
</tr>
<tr>
<td>2.420</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td style=" font-weight:bold;">ahb_communicate_inst/addr_reg_13_s0/Q</td>
</tr>
<tr>
<td>3.374</td>
<td>0.954</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td>ahb_communicate_inst/n335_s5/I1</td>
</tr>
<tr>
<td>3.929</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s5/F</td>
</tr>
<tr>
<td>4.176</td>
<td>0.247</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td>ahb_communicate_inst/n335_s4/I3</td>
</tr>
<tr>
<td>4.638</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s4/F</td>
</tr>
<tr>
<td>4.810</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C30[2][B]</td>
<td>ahb_communicate_inst/n335_s2/I3</td>
</tr>
<tr>
<td>5.263</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R26C30[2][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s2/F</td>
</tr>
<tr>
<td>5.682</td>
<td>0.419</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[0][A]</td>
<td>ahb_communicate_inst/hrdata_i_9_s1/I3</td>
</tr>
<tr>
<td>6.237</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R26C31[0][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_9_s1/F</td>
</tr>
<tr>
<td>6.938</td>
<td>0.701</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C28[2][B]</td>
<td>ahb_communicate_inst/hrdata_13_s6/I2</td>
</tr>
<tr>
<td>7.400</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R27C28[2][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_13_s6/F</td>
</tr>
<tr>
<td>7.400</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[2][B]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_13_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>37.719</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>38.928</td>
<td>1.209</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[2][B]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_13_s0/CLK</td>
</tr>
<tr>
<td>38.893</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R27C28[2][B]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_13_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.296</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>37.037</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 31.196%; route: 1.505, 68.804%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.487, 47.711%; route: 2.494, 47.838%; tC2Q: 0.232, 4.451%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 36.085%; route: 1.209, 63.915%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>31.535</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.476</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>39.010</td>
</tr>
<tr>
<td class="label">From</td>
<td>ahb_communicate_inst/addr_reg_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.188</td>
<td>1.505</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td>ahb_communicate_inst/addr_reg_13_s0/CLK</td>
</tr>
<tr>
<td>2.420</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td style=" font-weight:bold;">ahb_communicate_inst/addr_reg_13_s0/Q</td>
</tr>
<tr>
<td>3.374</td>
<td>0.954</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td>ahb_communicate_inst/n335_s5/I1</td>
</tr>
<tr>
<td>3.929</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s5/F</td>
</tr>
<tr>
<td>4.176</td>
<td>0.247</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td>ahb_communicate_inst/n335_s4/I3</td>
</tr>
<tr>
<td>4.638</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s4/F</td>
</tr>
<tr>
<td>4.810</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C30[2][B]</td>
<td>ahb_communicate_inst/n335_s2/I3</td>
</tr>
<tr>
<td>5.263</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R26C30[2][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s2/F</td>
</tr>
<tr>
<td>5.682</td>
<td>0.419</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[0][A]</td>
<td>ahb_communicate_inst/hrdata_i_9_s1/I3</td>
</tr>
<tr>
<td>6.237</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R26C31[0][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_9_s1/F</td>
</tr>
<tr>
<td>6.927</td>
<td>0.690</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C33[0][A]</td>
<td>ahb_communicate_inst/hrdata_i_7_s/I3</td>
</tr>
<tr>
<td>7.476</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R29C33[0][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_7_s/F</td>
</tr>
<tr>
<td>7.476</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C33[0][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_7_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>37.719</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>39.045</td>
<td>1.326</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C33[0][A]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_7_s0/CLK</td>
</tr>
<tr>
<td>39.010</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C33[0][A]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.179</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>37.037</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 31.196%; route: 1.505, 68.804%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.574, 48.675%; route: 2.482, 46.938%; tC2Q: 0.232, 4.387%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 33.982%; route: 1.326, 66.018%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>31.659</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.248</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>38.907</td>
</tr>
<tr>
<td class="label">From</td>
<td>ahb_communicate_inst/addr_reg_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_23_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.188</td>
<td>1.505</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td>ahb_communicate_inst/addr_reg_13_s0/CLK</td>
</tr>
<tr>
<td>2.420</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td style=" font-weight:bold;">ahb_communicate_inst/addr_reg_13_s0/Q</td>
</tr>
<tr>
<td>3.374</td>
<td>0.954</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td>ahb_communicate_inst/n335_s5/I1</td>
</tr>
<tr>
<td>3.929</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s5/F</td>
</tr>
<tr>
<td>4.176</td>
<td>0.247</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td>ahb_communicate_inst/n335_s4/I3</td>
</tr>
<tr>
<td>4.638</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s4/F</td>
</tr>
<tr>
<td>4.810</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C30[2][B]</td>
<td>ahb_communicate_inst/n335_s2/I3</td>
</tr>
<tr>
<td>5.263</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R26C30[2][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s2/F</td>
</tr>
<tr>
<td>5.682</td>
<td>0.419</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[0][A]</td>
<td>ahb_communicate_inst/hrdata_i_9_s1/I3</td>
</tr>
<tr>
<td>6.237</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R26C31[0][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_9_s1/F</td>
</tr>
<tr>
<td>6.678</td>
<td>0.441</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C29[1][B]</td>
<td>ahb_communicate_inst/hrdata_23_s7/I2</td>
</tr>
<tr>
<td>7.248</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R27C29[1][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_23_s7/F</td>
</tr>
<tr>
<td>7.248</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C29[1][B]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_23_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>37.719</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>38.942</td>
<td>1.223</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C29[1][B]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_23_s0/CLK</td>
</tr>
<tr>
<td>38.907</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R27C29[1][B]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_23_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.282</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>37.037</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 31.196%; route: 1.505, 68.804%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.595, 51.277%; route: 2.234, 44.138%; tC2Q: 0.232, 4.584%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 35.821%; route: 1.223, 64.179%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>31.661</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.329</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>38.989</td>
</tr>
<tr>
<td class="label">From</td>
<td>ahb_communicate_inst/addr_reg_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.188</td>
<td>1.505</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td>ahb_communicate_inst/addr_reg_13_s0/CLK</td>
</tr>
<tr>
<td>2.420</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td style=" font-weight:bold;">ahb_communicate_inst/addr_reg_13_s0/Q</td>
</tr>
<tr>
<td>3.374</td>
<td>0.954</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td>ahb_communicate_inst/n335_s5/I1</td>
</tr>
<tr>
<td>3.929</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s5/F</td>
</tr>
<tr>
<td>4.176</td>
<td>0.247</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td>ahb_communicate_inst/n335_s4/I3</td>
</tr>
<tr>
<td>4.638</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s4/F</td>
</tr>
<tr>
<td>4.810</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C30[2][B]</td>
<td>ahb_communicate_inst/n335_s2/I3</td>
</tr>
<tr>
<td>5.263</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R26C30[2][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s2/F</td>
</tr>
<tr>
<td>5.682</td>
<td>0.419</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[0][A]</td>
<td>ahb_communicate_inst/hrdata_i_9_s1/I3</td>
</tr>
<tr>
<td>6.237</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R26C31[0][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_9_s1/F</td>
</tr>
<tr>
<td>6.958</td>
<td>0.720</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C35[0][B]</td>
<td>ahb_communicate_inst/hrdata_i_4_s/I3</td>
</tr>
<tr>
<td>7.329</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R29C35[0][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_4_s/F</td>
</tr>
<tr>
<td>7.329</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C35[0][B]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_4_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>37.719</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>39.024</td>
<td>1.305</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C35[0][B]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_4_s0/CLK</td>
</tr>
<tr>
<td>38.989</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C35[0][B]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.200</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>37.037</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 31.196%; route: 1.505, 68.804%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.396, 46.607%; route: 2.513, 48.880%; tC2Q: 0.232, 4.513%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 34.342%; route: 1.305, 65.658%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>31.725</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.243</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>38.967</td>
</tr>
<tr>
<td class="label">From</td>
<td>ahb_communicate_inst/addr_reg_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.188</td>
<td>1.505</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td>ahb_communicate_inst/addr_reg_13_s0/CLK</td>
</tr>
<tr>
<td>2.420</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td style=" font-weight:bold;">ahb_communicate_inst/addr_reg_13_s0/Q</td>
</tr>
<tr>
<td>3.374</td>
<td>0.954</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td>ahb_communicate_inst/n335_s5/I1</td>
</tr>
<tr>
<td>3.929</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s5/F</td>
</tr>
<tr>
<td>4.176</td>
<td>0.247</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td>ahb_communicate_inst/n335_s4/I3</td>
</tr>
<tr>
<td>4.638</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s4/F</td>
</tr>
<tr>
<td>4.810</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C30[2][B]</td>
<td>ahb_communicate_inst/n335_s2/I3</td>
</tr>
<tr>
<td>5.263</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R26C30[2][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s2/F</td>
</tr>
<tr>
<td>5.682</td>
<td>0.419</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[0][A]</td>
<td>ahb_communicate_inst/hrdata_i_9_s1/I3</td>
</tr>
<tr>
<td>6.237</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R26C31[0][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_9_s1/F</td>
</tr>
<tr>
<td>6.673</td>
<td>0.436</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C31[0][B]</td>
<td>ahb_communicate_inst/hrdata_i_9_s/I3</td>
</tr>
<tr>
<td>7.243</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R29C31[0][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_9_s/F</td>
</tr>
<tr>
<td>7.243</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C31[0][B]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_9_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>37.719</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>39.002</td>
<td>1.283</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C31[0][B]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_9_s0/CLK</td>
</tr>
<tr>
<td>38.967</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C31[0][B]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.222</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>37.037</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 31.196%; route: 1.505, 68.804%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.595, 51.335%; route: 2.228, 44.075%; tC2Q: 0.232, 4.590%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 34.725%; route: 1.283, 65.275%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>31.740</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.227</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>38.967</td>
</tr>
<tr>
<td class="label">From</td>
<td>ahb_communicate_inst/addr_reg_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.188</td>
<td>1.505</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td>ahb_communicate_inst/addr_reg_13_s0/CLK</td>
</tr>
<tr>
<td>2.420</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td style=" font-weight:bold;">ahb_communicate_inst/addr_reg_13_s0/Q</td>
</tr>
<tr>
<td>3.374</td>
<td>0.954</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td>ahb_communicate_inst/n335_s5/I1</td>
</tr>
<tr>
<td>3.929</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s5/F</td>
</tr>
<tr>
<td>4.176</td>
<td>0.247</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td>ahb_communicate_inst/n335_s4/I3</td>
</tr>
<tr>
<td>4.638</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s4/F</td>
</tr>
<tr>
<td>4.810</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C30[2][B]</td>
<td>ahb_communicate_inst/n335_s2/I3</td>
</tr>
<tr>
<td>5.263</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R26C30[2][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s2/F</td>
</tr>
<tr>
<td>5.682</td>
<td>0.419</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[0][A]</td>
<td>ahb_communicate_inst/hrdata_i_9_s1/I3</td>
</tr>
<tr>
<td>6.237</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R26C31[0][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_9_s1/F</td>
</tr>
<tr>
<td>6.678</td>
<td>0.441</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C31[0][A]</td>
<td>ahb_communicate_inst/hrdata_i_5_s/I3</td>
</tr>
<tr>
<td>7.227</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R29C31[0][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_5_s/F</td>
</tr>
<tr>
<td>7.227</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C31[0][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_5_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>37.719</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>39.002</td>
<td>1.283</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C31[0][A]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_5_s0/CLK</td>
</tr>
<tr>
<td>38.967</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C31[0][A]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.222</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>37.037</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 31.196%; route: 1.505, 68.804%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.574, 51.074%; route: 2.234, 44.322%; tC2Q: 0.232, 4.603%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 34.725%; route: 1.283, 65.275%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>31.741</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.167</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>38.907</td>
</tr>
<tr>
<td class="label">From</td>
<td>ahb_communicate_inst/addr_reg_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_12_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.188</td>
<td>1.505</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td>ahb_communicate_inst/addr_reg_13_s0/CLK</td>
</tr>
<tr>
<td>2.420</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td style=" font-weight:bold;">ahb_communicate_inst/addr_reg_13_s0/Q</td>
</tr>
<tr>
<td>3.374</td>
<td>0.954</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td>ahb_communicate_inst/n335_s5/I1</td>
</tr>
<tr>
<td>3.929</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s5/F</td>
</tr>
<tr>
<td>4.176</td>
<td>0.247</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td>ahb_communicate_inst/n335_s4/I3</td>
</tr>
<tr>
<td>4.638</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s4/F</td>
</tr>
<tr>
<td>4.810</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C30[2][B]</td>
<td>ahb_communicate_inst/n335_s2/I3</td>
</tr>
<tr>
<td>5.263</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R26C30[2][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s2/F</td>
</tr>
<tr>
<td>5.682</td>
<td>0.419</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[0][A]</td>
<td>ahb_communicate_inst/hrdata_i_9_s1/I3</td>
</tr>
<tr>
<td>6.237</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R26C31[0][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_9_s1/F</td>
</tr>
<tr>
<td>6.705</td>
<td>0.468</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C29[0][A]</td>
<td>ahb_communicate_inst/hrdata_12_s6/I2</td>
</tr>
<tr>
<td>7.167</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R27C29[0][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_12_s6/F</td>
</tr>
<tr>
<td>7.167</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C29[0][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_12_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>37.719</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>38.942</td>
<td>1.223</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C29[0][A]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_12_s0/CLK</td>
</tr>
<tr>
<td>38.907</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R27C29[0][A]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_12_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.282</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>37.037</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 31.196%; route: 1.505, 68.804%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.487, 49.950%; route: 2.260, 45.390%; tC2Q: 0.232, 4.660%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 35.821%; route: 1.223, 64.179%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>31.741</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.167</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>38.907</td>
</tr>
<tr>
<td class="label">From</td>
<td>ahb_communicate_inst/addr_reg_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_10_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.188</td>
<td>1.505</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td>ahb_communicate_inst/addr_reg_13_s0/CLK</td>
</tr>
<tr>
<td>2.420</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td style=" font-weight:bold;">ahb_communicate_inst/addr_reg_13_s0/Q</td>
</tr>
<tr>
<td>3.374</td>
<td>0.954</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td>ahb_communicate_inst/n335_s5/I1</td>
</tr>
<tr>
<td>3.929</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s5/F</td>
</tr>
<tr>
<td>4.176</td>
<td>0.247</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td>ahb_communicate_inst/n335_s4/I3</td>
</tr>
<tr>
<td>4.638</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s4/F</td>
</tr>
<tr>
<td>4.810</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C30[2][B]</td>
<td>ahb_communicate_inst/n335_s2/I3</td>
</tr>
<tr>
<td>5.263</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R26C30[2][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s2/F</td>
</tr>
<tr>
<td>5.682</td>
<td>0.419</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[0][A]</td>
<td>ahb_communicate_inst/hrdata_i_9_s1/I3</td>
</tr>
<tr>
<td>6.237</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R26C31[0][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_9_s1/F</td>
</tr>
<tr>
<td>6.705</td>
<td>0.468</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C29[1][A]</td>
<td>ahb_communicate_inst/hrdata_10_s6/I2</td>
</tr>
<tr>
<td>7.167</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R27C29[1][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_10_s6/F</td>
</tr>
<tr>
<td>7.167</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C29[1][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_10_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>37.719</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>38.942</td>
<td>1.223</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C29[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_10_s0/CLK</td>
</tr>
<tr>
<td>38.907</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R27C29[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_10_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.282</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>37.037</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 31.196%; route: 1.505, 68.804%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.487, 49.950%; route: 2.260, 45.390%; tC2Q: 0.232, 4.660%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 35.821%; route: 1.223, 64.179%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>31.741</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.167</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>38.907</td>
</tr>
<tr>
<td class="label">From</td>
<td>ahb_communicate_inst/addr_reg_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_11_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.188</td>
<td>1.505</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td>ahb_communicate_inst/addr_reg_13_s0/CLK</td>
</tr>
<tr>
<td>2.420</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td style=" font-weight:bold;">ahb_communicate_inst/addr_reg_13_s0/Q</td>
</tr>
<tr>
<td>3.374</td>
<td>0.954</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td>ahb_communicate_inst/n335_s5/I1</td>
</tr>
<tr>
<td>3.929</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s5/F</td>
</tr>
<tr>
<td>4.176</td>
<td>0.247</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td>ahb_communicate_inst/n335_s4/I3</td>
</tr>
<tr>
<td>4.638</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s4/F</td>
</tr>
<tr>
<td>4.810</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C30[2][B]</td>
<td>ahb_communicate_inst/n335_s2/I3</td>
</tr>
<tr>
<td>5.263</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R26C30[2][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s2/F</td>
</tr>
<tr>
<td>5.682</td>
<td>0.419</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[0][A]</td>
<td>ahb_communicate_inst/hrdata_i_9_s1/I3</td>
</tr>
<tr>
<td>6.237</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R26C31[0][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_9_s1/F</td>
</tr>
<tr>
<td>6.705</td>
<td>0.468</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C29[0][B]</td>
<td>ahb_communicate_inst/hrdata_11_s6/I2</td>
</tr>
<tr>
<td>7.167</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R27C29[0][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_11_s6/F</td>
</tr>
<tr>
<td>7.167</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C29[0][B]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_11_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>37.719</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>38.942</td>
<td>1.223</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C29[0][B]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_11_s0/CLK</td>
</tr>
<tr>
<td>38.907</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R27C29[0][B]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_11_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.282</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>37.037</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 31.196%; route: 1.505, 68.804%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.487, 49.950%; route: 2.260, 45.390%; tC2Q: 0.232, 4.660%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 35.821%; route: 1.223, 64.179%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>31.741</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.167</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>38.907</td>
</tr>
<tr>
<td class="label">From</td>
<td>ahb_communicate_inst/addr_reg_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_22_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.188</td>
<td>1.505</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td>ahb_communicate_inst/addr_reg_13_s0/CLK</td>
</tr>
<tr>
<td>2.420</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td style=" font-weight:bold;">ahb_communicate_inst/addr_reg_13_s0/Q</td>
</tr>
<tr>
<td>3.374</td>
<td>0.954</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td>ahb_communicate_inst/n335_s5/I1</td>
</tr>
<tr>
<td>3.929</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s5/F</td>
</tr>
<tr>
<td>4.176</td>
<td>0.247</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td>ahb_communicate_inst/n335_s4/I3</td>
</tr>
<tr>
<td>4.638</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s4/F</td>
</tr>
<tr>
<td>4.810</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C30[2][B]</td>
<td>ahb_communicate_inst/n335_s2/I3</td>
</tr>
<tr>
<td>5.263</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R26C30[2][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s2/F</td>
</tr>
<tr>
<td>5.682</td>
<td>0.419</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[0][A]</td>
<td>ahb_communicate_inst/hrdata_i_9_s1/I3</td>
</tr>
<tr>
<td>6.237</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R26C31[0][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_9_s1/F</td>
</tr>
<tr>
<td>6.705</td>
<td>0.468</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C29[2][A]</td>
<td>ahb_communicate_inst/hrdata_22_s6/I2</td>
</tr>
<tr>
<td>7.167</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R27C29[2][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_22_s6/F</td>
</tr>
<tr>
<td>7.167</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C29[2][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_22_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>37.719</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>38.942</td>
<td>1.223</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C29[2][A]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_22_s0/CLK</td>
</tr>
<tr>
<td>38.907</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R27C29[2][A]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_22_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.282</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>37.037</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 31.196%; route: 1.505, 68.804%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.487, 49.950%; route: 2.260, 45.390%; tC2Q: 0.232, 4.660%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 35.821%; route: 1.223, 64.179%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>31.741</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.167</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>38.907</td>
</tr>
<tr>
<td class="label">From</td>
<td>ahb_communicate_inst/addr_reg_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_21_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.188</td>
<td>1.505</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td>ahb_communicate_inst/addr_reg_13_s0/CLK</td>
</tr>
<tr>
<td>2.420</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td style=" font-weight:bold;">ahb_communicate_inst/addr_reg_13_s0/Q</td>
</tr>
<tr>
<td>3.374</td>
<td>0.954</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td>ahb_communicate_inst/n335_s5/I1</td>
</tr>
<tr>
<td>3.929</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s5/F</td>
</tr>
<tr>
<td>4.176</td>
<td>0.247</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td>ahb_communicate_inst/n335_s4/I3</td>
</tr>
<tr>
<td>4.638</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s4/F</td>
</tr>
<tr>
<td>4.810</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C30[2][B]</td>
<td>ahb_communicate_inst/n335_s2/I3</td>
</tr>
<tr>
<td>5.263</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R26C30[2][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s2/F</td>
</tr>
<tr>
<td>5.682</td>
<td>0.419</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[0][A]</td>
<td>ahb_communicate_inst/hrdata_i_9_s1/I3</td>
</tr>
<tr>
<td>6.237</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R26C31[0][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_9_s1/F</td>
</tr>
<tr>
<td>6.705</td>
<td>0.468</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C29[2][B]</td>
<td>ahb_communicate_inst/hrdata_21_s6/I2</td>
</tr>
<tr>
<td>7.167</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R27C29[2][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_21_s6/F</td>
</tr>
<tr>
<td>7.167</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C29[2][B]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_21_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>37.719</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>38.942</td>
<td>1.223</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C29[2][B]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_21_s0/CLK</td>
</tr>
<tr>
<td>38.907</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R27C29[2][B]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_21_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.282</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>37.037</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 31.196%; route: 1.505, 68.804%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.487, 49.950%; route: 2.260, 45.390%; tC2Q: 0.232, 4.660%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 35.821%; route: 1.223, 64.179%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>31.748</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.392</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>39.140</td>
</tr>
<tr>
<td class="label">From</td>
<td>ahb_communicate_inst/addr_reg_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.188</td>
<td>1.505</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td>ahb_communicate_inst/addr_reg_13_s0/CLK</td>
</tr>
<tr>
<td>2.420</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td style=" font-weight:bold;">ahb_communicate_inst/addr_reg_13_s0/Q</td>
</tr>
<tr>
<td>3.374</td>
<td>0.954</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td>ahb_communicate_inst/n335_s5/I1</td>
</tr>
<tr>
<td>3.929</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s5/F</td>
</tr>
<tr>
<td>4.176</td>
<td>0.247</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td>ahb_communicate_inst/n335_s4/I3</td>
</tr>
<tr>
<td>4.638</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s4/F</td>
</tr>
<tr>
<td>4.810</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C30[2][B]</td>
<td>ahb_communicate_inst/n335_s2/I3</td>
</tr>
<tr>
<td>5.263</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R26C30[2][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s2/F</td>
</tr>
<tr>
<td>5.682</td>
<td>0.419</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[0][A]</td>
<td>ahb_communicate_inst/hrdata_i_9_s1/I3</td>
</tr>
<tr>
<td>6.237</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R26C31[0][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_9_s1/F</td>
</tr>
<tr>
<td>6.930</td>
<td>0.693</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C32[1][A]</td>
<td>ahb_communicate_inst/hrdata_i_6_s/I3</td>
</tr>
<tr>
<td>7.392</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R29C32[1][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_6_s/F</td>
</tr>
<tr>
<td>7.392</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C32[1][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_6_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>37.719</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>39.175</td>
<td>1.456</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C32[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_6_s0/CLK</td>
</tr>
<tr>
<td>39.140</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C32[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.050</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>37.037</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 31.196%; route: 1.505, 68.804%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.487, 47.786%; route: 2.485, 47.757%; tC2Q: 0.232, 4.458%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 31.921%; route: 1.456, 68.079%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>31.748</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.392</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>39.140</td>
</tr>
<tr>
<td class="label">From</td>
<td>ahb_communicate_inst/addr_reg_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.188</td>
<td>1.505</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td>ahb_communicate_inst/addr_reg_13_s0/CLK</td>
</tr>
<tr>
<td>2.420</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R25C46[0][A]</td>
<td style=" font-weight:bold;">ahb_communicate_inst/addr_reg_13_s0/Q</td>
</tr>
<tr>
<td>3.374</td>
<td>0.954</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td>ahb_communicate_inst/n335_s5/I1</td>
</tr>
<tr>
<td>3.929</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C32[2][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s5/F</td>
</tr>
<tr>
<td>4.176</td>
<td>0.247</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td>ahb_communicate_inst/n335_s4/I3</td>
</tr>
<tr>
<td>4.638</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C31[3][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s4/F</td>
</tr>
<tr>
<td>4.810</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C30[2][B]</td>
<td>ahb_communicate_inst/n335_s2/I3</td>
</tr>
<tr>
<td>5.263</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R26C30[2][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/n335_s2/F</td>
</tr>
<tr>
<td>5.682</td>
<td>0.419</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C31[0][A]</td>
<td>ahb_communicate_inst/hrdata_i_9_s1/I3</td>
</tr>
<tr>
<td>6.237</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R26C31[0][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_9_s1/F</td>
</tr>
<tr>
<td>6.930</td>
<td>0.693</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C32[1][B]</td>
<td>ahb_communicate_inst/hrdata_i_3_s/I3</td>
</tr>
<tr>
<td>7.392</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R29C32[1][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_3_s/F</td>
</tr>
<tr>
<td>7.392</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C32[1][B]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_3_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>37.719</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>39.175</td>
<td>1.456</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C32[1][B]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_3_s0/CLK</td>
</tr>
<tr>
<td>39.140</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C32[1][B]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.050</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>37.037</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 31.196%; route: 1.505, 68.804%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.487, 47.786%; route: 2.485, 47.757%; tC2Q: 0.232, 4.458%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 31.921%; route: 1.456, 68.079%</td>
</tr>
</table>
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
<h4>Report Command:report_timing -hold -from_clock [get_clocks {clk*}] -to_clock [get_clocks {clk*}] -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.044</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.061</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.017</td>
</tr>
<tr>
<td class="label">From</td>
<td>Gowin_PicoRV32_Top_inst/wb/wbm_dat_o_15_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/wbuart_ins/uart_setup_15_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.598</td>
<td>0.923</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C51[2][B]</td>
<td>Gowin_PicoRV32_Top_inst/wb/wbm_dat_o_15_s0/CLK</td>
</tr>
<tr>
<td>1.800</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R18C51[2][B]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/wb/wbm_dat_o_15_s0/Q</td>
</tr>
<tr>
<td>2.061</td>
<td>0.260</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C52[0][B]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/wbuart_ins/uart_setup_15_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.006</td>
<td>1.331</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C52[0][B]</td>
<td>Gowin_PicoRV32_Top_inst/wbuart_ins/uart_setup_15_s1/CLK</td>
</tr>
<tr>
<td>2.017</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C52[0][B]</td>
<td>Gowin_PicoRV32_Top_inst/wbuart_ins/uart_setup_15_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.408</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 42.261%; route: 0.923, 57.739%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 33.672%; route: 1.331, 66.328%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.425</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.470</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.033</td>
<td>1.358</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C53[1][A]</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>2.235</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R31C53[1][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst1/clk_cnt_2_s0/Q</td>
</tr>
<tr>
<td>2.238</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R31C53[1][A]</td>
<td>mic_serial_inst/mic_sample_inst1/n23_s/I1</td>
</tr>
<tr>
<td>2.470</td>
<td>0.232</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R31C53[1][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/mic_sample_inst1/n23_s/SUM</td>
</tr>
<tr>
<td>2.470</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R31C53[1][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst1/clk_cnt_2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.033</td>
<td>1.358</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C53[1][A]</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>2.044</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R31C53[1][A]</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 33.224%; route: 1.358, 66.776%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 33.224%; route: 1.358, 66.776%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.425</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.467</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.042</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_6_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.031</td>
<td>1.355</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R36C45[0][A]</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_6_s0/CLK</td>
</tr>
<tr>
<td>2.233</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R36C45[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst3/clk_cnt_6_s0/Q</td>
</tr>
<tr>
<td>2.235</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R36C45[0][A]</td>
<td>mic_serial_inst/mic_sample_inst3/n19_s/I1</td>
</tr>
<tr>
<td>2.467</td>
<td>0.232</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R36C45[0][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/mic_sample_inst3/n19_s/SUM</td>
</tr>
<tr>
<td>2.467</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R36C45[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst3/clk_cnt_6_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.031</td>
<td>1.355</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R36C45[0][A]</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_6_s0/CLK</td>
</tr>
<tr>
<td>2.042</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R36C45[0][A]</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 33.262%; route: 1.355, 66.738%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 33.262%; route: 1.355, 66.738%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.425</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.485</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.060</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.049</td>
<td>1.373</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C52[1][A]</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>2.251</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R35C52[1][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst2/clk_cnt_2_s0/Q</td>
</tr>
<tr>
<td>2.253</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R35C52[1][A]</td>
<td>mic_serial_inst/mic_sample_inst2/n23_s/I1</td>
</tr>
<tr>
<td>2.485</td>
<td>0.232</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R35C52[1][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/mic_sample_inst2/n23_s/SUM</td>
</tr>
<tr>
<td>2.485</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R35C52[1][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst2/clk_cnt_2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.049</td>
<td>1.373</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C52[1][A]</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>2.060</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R35C52[1][A]</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 32.971%; route: 1.373, 67.029%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 32.971%; route: 1.373, 67.029%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.425</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.473</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.047</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_6_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.036</td>
<td>1.361</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C53[0][A]</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_6_s0/CLK</td>
</tr>
<tr>
<td>2.238</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R35C53[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst2/clk_cnt_6_s0/Q</td>
</tr>
<tr>
<td>2.241</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R35C53[0][A]</td>
<td>mic_serial_inst/mic_sample_inst2/n19_s/I1</td>
</tr>
<tr>
<td>2.473</td>
<td>0.232</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R35C53[0][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/mic_sample_inst2/n19_s/SUM</td>
</tr>
<tr>
<td>2.473</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R35C53[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst2/clk_cnt_6_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.036</td>
<td>1.361</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C53[0][A]</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_6_s0/CLK</td>
</tr>
<tr>
<td>2.047</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R35C53[0][A]</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 33.175%; route: 1.361, 66.825%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 33.175%; route: 1.361, 66.825%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.425</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.469</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.043</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.032</td>
<td>1.357</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R36C44[1][A]</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>2.234</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R36C44[1][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst3/clk_cnt_2_s0/Q</td>
</tr>
<tr>
<td>2.237</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R36C44[1][A]</td>
<td>mic_serial_inst/mic_sample_inst3/n23_s/I1</td>
</tr>
<tr>
<td>2.469</td>
<td>0.232</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R36C44[1][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/mic_sample_inst3/n23_s/SUM</td>
</tr>
<tr>
<td>2.469</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R36C44[1][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst3/clk_cnt_2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.032</td>
<td>1.357</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R36C44[1][A]</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>2.043</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R36C44[1][A]</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 33.241%; route: 1.357, 66.759%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 33.241%; route: 1.357, 66.759%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.427</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.494</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.068</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_6_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.057</td>
<td>1.381</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C54[0][A]</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_6_s0/CLK</td>
</tr>
<tr>
<td>2.259</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R31C54[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst1/clk_cnt_6_s0/Q</td>
</tr>
<tr>
<td>2.262</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R31C54[0][A]</td>
<td>mic_serial_inst/mic_sample_inst1/n19_s/I1</td>
</tr>
<tr>
<td>2.494</td>
<td>0.232</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R31C54[0][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/mic_sample_inst1/n19_s/SUM</td>
</tr>
<tr>
<td>2.494</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R31C54[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst1/clk_cnt_6_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.057</td>
<td>1.381</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C54[0][A]</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_6_s0/CLK</td>
</tr>
<tr>
<td>2.068</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R31C54[0][A]</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 32.844%; route: 1.381, 67.156%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 32.844%; route: 1.381, 67.156%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.546</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.593</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.047</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_7_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.036</td>
<td>1.361</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C53[0][B]</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_7_s0/CLK</td>
</tr>
<tr>
<td>2.237</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>4</td>
<td>R35C53[0][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst2/clk_cnt_7_s0/Q</td>
</tr>
<tr>
<td>2.361</td>
<td>0.124</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R35C53[0][B]</td>
<td>mic_serial_inst/mic_sample_inst2/n18_s/I1</td>
</tr>
<tr>
<td>2.593</td>
<td>0.232</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R35C53[0][B]</td>
<td style=" background: #97FFFF;">mic_serial_inst/mic_sample_inst2/n18_s/SUM</td>
</tr>
<tr>
<td>2.593</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R35C53[0][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst2/clk_cnt_7_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.036</td>
<td>1.361</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C53[0][B]</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_7_s0/CLK</td>
</tr>
<tr>
<td>2.047</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R35C53[0][B]</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 33.175%; route: 1.361, 66.825%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 41.687%; route: 0.124, 22.197%; tC2Q: 0.201, 36.117%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 33.175%; route: 1.361, 66.825%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.546</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.590</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.033</td>
<td>1.358</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C53[2][A]</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>2.234</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R31C53[2][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst1/clk_cnt_4_s0/Q</td>
</tr>
<tr>
<td>2.358</td>
<td>0.124</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R31C53[2][A]</td>
<td>mic_serial_inst/mic_sample_inst1/n21_s/I1</td>
</tr>
<tr>
<td>2.590</td>
<td>0.232</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R31C53[2][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/mic_sample_inst1/n21_s/SUM</td>
</tr>
<tr>
<td>2.590</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R31C53[2][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst1/clk_cnt_4_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.033</td>
<td>1.358</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C53[2][A]</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>2.044</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R31C53[2][A]</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 33.224%; route: 1.358, 66.776%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 41.676%; route: 0.124, 22.216%; tC2Q: 0.201, 36.107%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 33.224%; route: 1.358, 66.776%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.546</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.605</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.060</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.049</td>
<td>1.373</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C52[2][A]</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>2.250</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R35C52[2][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst2/clk_cnt_4_s0/Q</td>
</tr>
<tr>
<td>2.373</td>
<td>0.124</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R35C52[2][A]</td>
<td>mic_serial_inst/mic_sample_inst2/n21_s/I1</td>
</tr>
<tr>
<td>2.605</td>
<td>0.232</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R35C52[2][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/mic_sample_inst2/n21_s/SUM</td>
</tr>
<tr>
<td>2.605</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R35C52[2][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst2/clk_cnt_4_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.049</td>
<td>1.373</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C52[2][A]</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>2.060</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R35C52[2][A]</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 32.971%; route: 1.373, 67.029%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 41.676%; route: 0.124, 22.216%; tC2Q: 0.201, 36.107%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 32.971%; route: 1.373, 67.029%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.546</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.590</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.033</td>
<td>1.358</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C53[1][B]</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>2.234</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R31C53[1][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst1/clk_cnt_3_s0/Q</td>
</tr>
<tr>
<td>2.358</td>
<td>0.124</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R31C53[1][B]</td>
<td>mic_serial_inst/mic_sample_inst1/n22_s/I1</td>
</tr>
<tr>
<td>2.590</td>
<td>0.232</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R31C53[1][B]</td>
<td style=" background: #97FFFF;">mic_serial_inst/mic_sample_inst1/n22_s/SUM</td>
</tr>
<tr>
<td>2.590</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R31C53[1][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst1/clk_cnt_3_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.033</td>
<td>1.358</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C53[1][B]</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>2.044</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R31C53[1][B]</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 33.224%; route: 1.358, 66.776%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 41.676%; route: 0.124, 22.216%; tC2Q: 0.201, 36.107%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 33.224%; route: 1.358, 66.776%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.546</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.605</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.060</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.049</td>
<td>1.373</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C52[1][B]</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>2.250</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R35C52[1][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst2/clk_cnt_3_s0/Q</td>
</tr>
<tr>
<td>2.373</td>
<td>0.124</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R35C52[1][B]</td>
<td>mic_serial_inst/mic_sample_inst2/n22_s/I1</td>
</tr>
<tr>
<td>2.605</td>
<td>0.232</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R35C52[1][B]</td>
<td style=" background: #97FFFF;">mic_serial_inst/mic_sample_inst2/n22_s/SUM</td>
</tr>
<tr>
<td>2.605</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R35C52[1][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst2/clk_cnt_3_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.049</td>
<td>1.373</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C52[1][B]</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>2.060</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R35C52[1][B]</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 32.971%; route: 1.373, 67.029%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 41.676%; route: 0.124, 22.216%; tC2Q: 0.201, 36.107%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 32.971%; route: 1.373, 67.029%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.546</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.589</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.043</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.032</td>
<td>1.357</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R36C44[2][A]</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>2.233</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R36C44[2][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst3/clk_cnt_4_s0/Q</td>
</tr>
<tr>
<td>2.357</td>
<td>0.124</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R36C44[2][A]</td>
<td>mic_serial_inst/mic_sample_inst3/n21_s/I1</td>
</tr>
<tr>
<td>2.589</td>
<td>0.232</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R36C44[2][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/mic_sample_inst3/n21_s/SUM</td>
</tr>
<tr>
<td>2.589</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R36C44[2][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst3/clk_cnt_4_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.032</td>
<td>1.357</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R36C44[2][A]</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>2.043</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R36C44[2][A]</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 33.241%; route: 1.357, 66.759%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 41.676%; route: 0.124, 22.216%; tC2Q: 0.201, 36.107%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 33.241%; route: 1.357, 66.759%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.546</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.589</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.043</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.032</td>
<td>1.357</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R36C44[1][B]</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>2.233</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R36C44[1][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst3/clk_cnt_3_s0/Q</td>
</tr>
<tr>
<td>2.357</td>
<td>0.124</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R36C44[1][B]</td>
<td>mic_serial_inst/mic_sample_inst3/n22_s/I1</td>
</tr>
<tr>
<td>2.589</td>
<td>0.232</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R36C44[1][B]</td>
<td style=" background: #97FFFF;">mic_serial_inst/mic_sample_inst3/n22_s/SUM</td>
</tr>
<tr>
<td>2.589</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R36C44[1][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst3/clk_cnt_3_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.032</td>
<td>1.357</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R36C44[1][B]</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>2.043</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R36C44[1][B]</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 33.241%; route: 1.357, 66.759%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 41.676%; route: 0.124, 22.216%; tC2Q: 0.201, 36.107%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 33.241%; route: 1.357, 66.759%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.547</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.590</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.043</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.032</td>
<td>1.357</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R36C44[2][B]</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_5_s0/CLK</td>
</tr>
<tr>
<td>2.233</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R36C44[2][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst3/clk_cnt_5_s0/Q</td>
</tr>
<tr>
<td>2.358</td>
<td>0.125</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R36C44[2][B]</td>
<td>mic_serial_inst/mic_sample_inst3/n20_s/I1</td>
</tr>
<tr>
<td>2.590</td>
<td>0.232</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R36C44[2][B]</td>
<td style=" background: #97FFFF;">mic_serial_inst/mic_sample_inst3/n20_s/SUM</td>
</tr>
<tr>
<td>2.590</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R36C44[2][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst3/clk_cnt_5_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.032</td>
<td>1.357</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R36C44[2][B]</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_5_s0/CLK</td>
</tr>
<tr>
<td>2.043</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R36C44[2][B]</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 33.241%; route: 1.357, 66.759%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 41.564%; route: 0.125, 22.426%; tC2Q: 0.201, 36.010%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 33.241%; route: 1.357, 66.759%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.547</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.607</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.060</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.049</td>
<td>1.373</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C52[2][B]</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_5_s0/CLK</td>
</tr>
<tr>
<td>2.250</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R35C52[2][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst2/clk_cnt_5_s0/Q</td>
</tr>
<tr>
<td>2.375</td>
<td>0.125</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R35C52[2][B]</td>
<td>mic_serial_inst/mic_sample_inst2/n20_s/I1</td>
</tr>
<tr>
<td>2.607</td>
<td>0.232</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R35C52[2][B]</td>
<td style=" background: #97FFFF;">mic_serial_inst/mic_sample_inst2/n20_s/SUM</td>
</tr>
<tr>
<td>2.607</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R35C52[2][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst2/clk_cnt_5_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.049</td>
<td>1.373</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C52[2][B]</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_5_s0/CLK</td>
</tr>
<tr>
<td>2.060</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R35C52[2][B]</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 32.971%; route: 1.373, 67.029%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 41.564%; route: 0.125, 22.426%; tC2Q: 0.201, 36.010%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 32.971%; route: 1.373, 67.029%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.550</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.595</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.033</td>
<td>1.358</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C53[2][B]</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_5_s0/CLK</td>
</tr>
<tr>
<td>2.234</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R31C53[2][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst1/clk_cnt_5_s0/Q</td>
</tr>
<tr>
<td>2.363</td>
<td>0.128</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R31C53[2][B]</td>
<td>mic_serial_inst/mic_sample_inst1/n20_s/I1</td>
</tr>
<tr>
<td>2.595</td>
<td>0.232</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R31C53[2][B]</td>
<td style=" background: #97FFFF;">mic_serial_inst/mic_sample_inst1/n20_s/SUM</td>
</tr>
<tr>
<td>2.595</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R31C53[2][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst1/clk_cnt_5_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.033</td>
<td>1.358</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C53[2][B]</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_5_s0/CLK</td>
</tr>
<tr>
<td>2.044</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R31C53[2][B]</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 33.224%; route: 1.358, 66.776%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 41.321%; route: 0.128, 22.879%; tC2Q: 0.201, 35.800%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 33.224%; route: 1.358, 66.776%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.656</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.698</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.042</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_6_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.031</td>
<td>1.355</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R36C45[0][A]</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_6_s0/CLK</td>
</tr>
<tr>
<td>2.233</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R36C45[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst3/clk_cnt_6_s0/Q</td>
</tr>
<tr>
<td>2.235</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R36C45[0][A]</td>
<td>mic_serial_inst/mic_sample_inst3/n19_s/I1</td>
</tr>
<tr>
<td>2.467</td>
<td>0.232</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R36C45[0][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/mic_sample_inst3/n19_s/COUT</td>
</tr>
<tr>
<td>2.467</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R36C45[0][B]</td>
<td>mic_serial_inst/mic_sample_inst3/n18_s/CIN</td>
</tr>
<tr>
<td>2.698</td>
<td>0.231</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R36C45[0][B]</td>
<td style=" background: #97FFFF;">mic_serial_inst/mic_sample_inst3/n18_s/SUM</td>
</tr>
<tr>
<td>2.698</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R36C45[0][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst3/clk_cnt_7_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.031</td>
<td>1.355</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R36C45[0][B]</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_7_s0/CLK</td>
</tr>
<tr>
<td>2.042</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R36C45[0][B]</td>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 33.262%; route: 1.355, 66.738%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.463, 69.369%; route: 0.002, 0.366%; tC2Q: 0.202, 30.265%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 33.262%; route: 1.355, 66.738%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.658</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.725</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.068</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_6_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.057</td>
<td>1.381</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C54[0][A]</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_6_s0/CLK</td>
</tr>
<tr>
<td>2.259</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R31C54[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst1/clk_cnt_6_s0/Q</td>
</tr>
<tr>
<td>2.262</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R31C54[0][A]</td>
<td>mic_serial_inst/mic_sample_inst1/n19_s/I1</td>
</tr>
<tr>
<td>2.494</td>
<td>0.232</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R31C54[0][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/mic_sample_inst1/n19_s/COUT</td>
</tr>
<tr>
<td>2.494</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R31C54[0][B]</td>
<td>mic_serial_inst/mic_sample_inst1/n18_s/CIN</td>
</tr>
<tr>
<td>2.725</td>
<td>0.231</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R31C54[0][B]</td>
<td style=" background: #97FFFF;">mic_serial_inst/mic_sample_inst1/n18_s/SUM</td>
</tr>
<tr>
<td>2.725</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R31C54[0][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_sample_inst1/clk_cnt_7_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.057</td>
<td>1.381</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C54[0][B]</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_7_s0/CLK</td>
</tr>
<tr>
<td>2.068</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R31C54[0][B]</td>
<td>mic_serial_inst/mic_sample_inst1/clk_cnt_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 32.844%; route: 1.381, 67.156%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.463, 69.242%; route: 0.004, 0.548%; tC2Q: 0.202, 30.209%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 32.844%; route: 1.381, 67.156%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.671</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.396</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.725</td>
</tr>
<tr>
<td class="label">From</td>
<td>ahb_communicate_inst/addr_reg_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.575</td>
<td>0.899</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C30[2][A]</td>
<td>ahb_communicate_inst/addr_reg_2_s0/CLK</td>
</tr>
<tr>
<td>1.777</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>25</td>
<td>R26C30[2][A]</td>
<td style=" font-weight:bold;">ahb_communicate_inst/addr_reg_2_s0/Q</td>
</tr>
<tr>
<td>2.164</td>
<td>0.387</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C32[1][B]</td>
<td>ahb_communicate_inst/hrdata_i_3_s/I2</td>
</tr>
<tr>
<td>2.396</td>
<td>0.232</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R29C32[1][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_3_s/F</td>
</tr>
<tr>
<td>2.396</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C32[1][B]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_3_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.714</td>
<td>1.039</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C32[1][B]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_3_s0/CLK</td>
</tr>
<tr>
<td>1.725</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R29C32[1][B]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.140</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 42.895%; route: 0.899, 57.105%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 28.249%; route: 0.387, 47.156%; tC2Q: 0.202, 24.596%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 39.404%; route: 1.039, 60.596%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.707</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.276</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.569</td>
</tr>
<tr>
<td class="label">From</td>
<td>ahb_communicate_inst/addr_reg_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.575</td>
<td>0.899</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C30[2][A]</td>
<td>ahb_communicate_inst/addr_reg_2_s0/CLK</td>
</tr>
<tr>
<td>1.777</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>25</td>
<td>R26C30[2][A]</td>
<td style=" font-weight:bold;">ahb_communicate_inst/addr_reg_2_s0/Q</td>
</tr>
<tr>
<td>2.044</td>
<td>0.268</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[1][A]</td>
<td>ahb_communicate_inst/hrdata_i_0_s/I2</td>
</tr>
<tr>
<td>2.276</td>
<td>0.232</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R27C28[1][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_0_s/F</td>
</tr>
<tr>
<td>2.276</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C28[1][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_0_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.558</td>
<td>0.883</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_0_s0/CLK</td>
</tr>
<tr>
<td>1.569</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R27C28[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.016</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 42.895%; route: 0.899, 57.105%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 33.067%; route: 0.268, 38.142%; tC2Q: 0.202, 28.791%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 43.346%; route: 0.883, 56.654%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.806</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.532</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.725</td>
</tr>
<tr>
<td class="label">From</td>
<td>ahb_communicate_inst/addr_reg_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.575</td>
<td>0.899</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C30[2][A]</td>
<td>ahb_communicate_inst/addr_reg_2_s0/CLK</td>
</tr>
<tr>
<td>1.777</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>25</td>
<td>R26C30[2][A]</td>
<td style=" font-weight:bold;">ahb_communicate_inst/addr_reg_2_s0/Q</td>
</tr>
<tr>
<td>2.168</td>
<td>0.391</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C32[1][A]</td>
<td>ahb_communicate_inst/hrdata_i_6_s/I2</td>
</tr>
<tr>
<td>2.532</td>
<td>0.364</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R29C32[1][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_6_s/F</td>
</tr>
<tr>
<td>2.532</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C32[1][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_6_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.714</td>
<td>1.039</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C32[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_6_s0/CLK</td>
</tr>
<tr>
<td>1.725</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R29C32[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.140</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 42.895%; route: 0.899, 57.105%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.364, 38.044%; route: 0.391, 40.843%; tC2Q: 0.202, 21.113%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 39.404%; route: 1.039, 60.596%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.821</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.431</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.610</td>
</tr>
<tr>
<td class="label">From</td>
<td>ahb_communicate_inst/addr_reg_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.575</td>
<td>0.899</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C30[2][A]</td>
<td>ahb_communicate_inst/addr_reg_2_s0/CLK</td>
</tr>
<tr>
<td>1.777</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>25</td>
<td>R26C30[2][A]</td>
<td style=" font-weight:bold;">ahb_communicate_inst/addr_reg_2_s0/Q</td>
</tr>
<tr>
<td>2.199</td>
<td>0.422</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C34[0][B]</td>
<td>ahb_communicate_inst/hrdata_i_2_s/I2</td>
</tr>
<tr>
<td>2.431</td>
<td>0.232</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R29C34[0][B]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_2_s/F</td>
</tr>
<tr>
<td>2.431</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C34[0][B]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.599</td>
<td>0.924</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C34[0][B]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_2_s0/CLK</td>
</tr>
<tr>
<td>1.610</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R29C34[0][B]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.024</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 42.895%; route: 0.899, 57.105%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 27.099%; route: 0.422, 49.306%; tC2Q: 0.202, 23.595%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 42.241%; route: 0.924, 57.759%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.821</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.431</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.610</td>
</tr>
<tr>
<td class="label">From</td>
<td>ahb_communicate_inst/addr_reg_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.575</td>
<td>0.899</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C30[2][A]</td>
<td>ahb_communicate_inst/addr_reg_2_s0/CLK</td>
</tr>
<tr>
<td>1.777</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>25</td>
<td>R26C30[2][A]</td>
<td style=" font-weight:bold;">ahb_communicate_inst/addr_reg_2_s0/Q</td>
</tr>
<tr>
<td>2.199</td>
<td>0.422</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C34[0][A]</td>
<td>ahb_communicate_inst/hrdata_i_8_s/I2</td>
</tr>
<tr>
<td>2.431</td>
<td>0.232</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R29C34[0][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_8_s/F</td>
</tr>
<tr>
<td>2.431</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C34[0][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_8_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.599</td>
<td>0.924</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C34[0][A]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_8_s0/CLK</td>
</tr>
<tr>
<td>1.610</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R29C34[0][A]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_8_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.024</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 42.895%; route: 0.899, 57.105%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 27.099%; route: 0.422, 49.306%; tC2Q: 0.202, 23.595%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 42.241%; route: 0.924, 57.759%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.825</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.398</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.574</td>
</tr>
<tr>
<td class="label">From</td>
<td>ahb_communicate_inst/addr_reg_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.575</td>
<td>0.899</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C30[2][A]</td>
<td>ahb_communicate_inst/addr_reg_2_s0/CLK</td>
</tr>
<tr>
<td>1.777</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>25</td>
<td>R26C30[2][A]</td>
<td style=" font-weight:bold;">ahb_communicate_inst/addr_reg_2_s0/Q</td>
</tr>
<tr>
<td>2.166</td>
<td>0.390</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C31[0][A]</td>
<td>ahb_communicate_inst/hrdata_i_5_s/I2</td>
</tr>
<tr>
<td>2.398</td>
<td>0.232</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R29C31[0][A]</td>
<td style=" background: #97FFFF;">ahb_communicate_inst/hrdata_i_5_s/F</td>
</tr>
<tr>
<td>2.398</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C31[0][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_5_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.563</td>
<td>0.887</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C31[0][A]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_5_s0/CLK</td>
</tr>
<tr>
<td>1.574</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R29C31[0][A]</td>
<td>Gowin_PicoRV32_Top_inst/ahb_interface/mem_rdata_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.012</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 42.895%; route: 0.899, 57.105%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 28.169%; route: 0.390, 47.305%; tC2Q: 0.202, 24.526%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 43.222%; route: 0.887, 56.778%</td>
</tr>
</table>
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.611</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>543.455</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>540.844</td>
</tr>
<tr>
<td class="label">From</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>540.000</td>
<td>540.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>540.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>540.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1657</td>
<td>BOTTOMSIDE[0]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>540.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R43C20[2][A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK</td>
</tr>
<tr>
<td>540.815</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>585</td>
<td>R43C20[2][A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
</tr>
<tr>
<td>543.455</td>
<td>2.640</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R30C25[0][B]</td>
<td style=" font-weight:bold;">Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_8_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>540.123</td>
<td>540.123</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>540.123</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_clkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>540.671</td>
<td>0.548</td>
<td>tCL</td>
<td>RR</td>
<td>327</td>
<td>TOPSIDE[0]</td>
<td>u_clkdiv/CLKOUT</td>
</tr>
<tr>
<td>540.914</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C25[0][B]</td>
<td>Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_8_s0/CLK</td>
</tr>
<tr>
<td>540.879</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_8_s0</td>
</tr>
<tr>
<td>540.844</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R30C25[0][B]</td>
<td>Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_8_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.208</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.123</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.640, 91.922%; tC2Q: 0.232, 8.078%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.611</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>543.455</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>540.844</td>
</tr>
<tr>
<td class="label">From</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_11_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>540.000</td>
<td>540.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>540.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>540.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1657</td>
<td>BOTTOMSIDE[0]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>540.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R43C20[2][A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK</td>
</tr>
<tr>
<td>540.815</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>585</td>
<td>R43C20[2][A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
</tr>
<tr>
<td>543.455</td>
<td>2.640</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R30C25[0][A]</td>
<td style=" font-weight:bold;">Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_11_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>540.123</td>
<td>540.123</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>540.123</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_clkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>540.671</td>
<td>0.548</td>
<td>tCL</td>
<td>RR</td>
<td>327</td>
<td>TOPSIDE[0]</td>
<td>u_clkdiv/CLKOUT</td>
</tr>
<tr>
<td>540.914</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C25[0][A]</td>
<td>Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_11_s0/CLK</td>
</tr>
<tr>
<td>540.879</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_11_s0</td>
</tr>
<tr>
<td>540.844</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R30C25[0][A]</td>
<td>Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_11_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.208</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.123</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.640, 91.922%; tC2Q: 0.232, 8.078%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.542</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1252.592</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1250.050</td>
</tr>
<tr>
<td class="label">From</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1249.999</td>
<td>1249.999</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1249.999</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_clkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.546</td>
<td>0.548</td>
<td>tCL</td>
<td>RR</td>
<td>327</td>
<td>TOPSIDE[0]</td>
<td>u_clkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.790</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C24[0][A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK</td>
</tr>
<tr>
<td>1251.022</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1189</td>
<td>R34C24[0][A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1252.592</td>
<td>1.570</td>
<td>tNET</td>
<td>FF</td>
<td>10</td>
<td>R56C45</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1250.000</td>
<td>1250.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1250.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1657</td>
<td>BOTTOMSIDE[0]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R56C45</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/PCLK</td>
</tr>
<tr>
<td>1250.548</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs</td>
</tr>
<tr>
<td>1250.050</td>
<td>-0.498</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R56C45</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.208</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.001</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.542</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1252.592</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1250.050</td>
</tr>
<tr>
<td class="label">From</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1249.999</td>
<td>1249.999</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1249.999</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_clkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.546</td>
<td>0.548</td>
<td>tCL</td>
<td>RR</td>
<td>327</td>
<td>TOPSIDE[0]</td>
<td>u_clkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.790</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C24[0][A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK</td>
</tr>
<tr>
<td>1251.022</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1189</td>
<td>R34C24[0][A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1252.592</td>
<td>1.570</td>
<td>tNET</td>
<td>FF</td>
<td>10</td>
<td>R56C12</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1250.000</td>
<td>1250.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1250.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1657</td>
<td>BOTTOMSIDE[0]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R56C12</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/PCLK</td>
</tr>
<tr>
<td>1250.548</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs</td>
</tr>
<tr>
<td>1250.050</td>
<td>-0.498</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R56C12</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.208</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.001</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.376</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>543.220</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>540.844</td>
</tr>
<tr>
<td class="label">From</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>540.000</td>
<td>540.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>540.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>540.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1657</td>
<td>BOTTOMSIDE[0]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>540.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R43C20[2][A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK</td>
</tr>
<tr>
<td>540.815</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>585</td>
<td>R43C20[2][A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
</tr>
<tr>
<td>543.220</td>
<td>2.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C26[0][B]</td>
<td style=" font-weight:bold;">Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_9_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>540.123</td>
<td>540.123</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>540.123</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_clkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>540.671</td>
<td>0.548</td>
<td>tCL</td>
<td>RR</td>
<td>327</td>
<td>TOPSIDE[0]</td>
<td>u_clkdiv/CLKOUT</td>
</tr>
<tr>
<td>540.914</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C26[0][B]</td>
<td>Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_9_s0/CLK</td>
</tr>
<tr>
<td>540.879</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_9_s0</td>
</tr>
<tr>
<td>540.844</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C26[0][B]</td>
<td>Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.208</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.123</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.405, 91.202%; tC2Q: 0.232, 8.798%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.376</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>543.220</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>540.844</td>
</tr>
<tr>
<td class="label">From</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_10_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>540.000</td>
<td>540.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>540.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>540.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1657</td>
<td>BOTTOMSIDE[0]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>540.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R43C20[2][A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK</td>
</tr>
<tr>
<td>540.815</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>585</td>
<td>R43C20[2][A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
</tr>
<tr>
<td>543.220</td>
<td>2.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C26[0][A]</td>
<td style=" font-weight:bold;">Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_10_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>540.123</td>
<td>540.123</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>540.123</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_clkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>540.671</td>
<td>0.548</td>
<td>tCL</td>
<td>RR</td>
<td>327</td>
<td>TOPSIDE[0]</td>
<td>u_clkdiv/CLKOUT</td>
</tr>
<tr>
<td>540.914</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C26[0][A]</td>
<td>Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_10_s0/CLK</td>
</tr>
<tr>
<td>540.879</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_10_s0</td>
</tr>
<tr>
<td>540.844</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C26[0][A]</td>
<td>Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_10_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.208</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.123</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.405, 91.202%; tC2Q: 0.232, 8.798%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.376</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>543.220</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>540.844</td>
</tr>
<tr>
<td class="label">From</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_25_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>540.000</td>
<td>540.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>540.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>540.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1657</td>
<td>BOTTOMSIDE[0]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>540.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R43C20[2][A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK</td>
</tr>
<tr>
<td>540.815</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>585</td>
<td>R43C20[2][A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
</tr>
<tr>
<td>543.220</td>
<td>2.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C26[2][B]</td>
<td style=" font-weight:bold;">Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_25_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>540.123</td>
<td>540.123</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>540.123</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_clkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>540.671</td>
<td>0.548</td>
<td>tCL</td>
<td>RR</td>
<td>327</td>
<td>TOPSIDE[0]</td>
<td>u_clkdiv/CLKOUT</td>
</tr>
<tr>
<td>540.914</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C26[2][B]</td>
<td>Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_25_s0/CLK</td>
</tr>
<tr>
<td>540.879</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_25_s0</td>
</tr>
<tr>
<td>540.844</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C26[2][B]</td>
<td>Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_25_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.208</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.123</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.405, 91.202%; tC2Q: 0.232, 8.798%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.197</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1252.592</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1250.395</td>
</tr>
<tr>
<td class="label">From</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/u_ck_gen</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1249.999</td>
<td>1249.999</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1249.999</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_clkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.546</td>
<td>0.548</td>
<td>tCL</td>
<td>RR</td>
<td>327</td>
<td>TOPSIDE[0]</td>
<td>u_clkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.790</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C24[0][A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK</td>
</tr>
<tr>
<td>1251.022</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1189</td>
<td>R34C24[0][A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1252.592</td>
<td>1.570</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>IOB27[A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/u_ck_gen/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1250.000</td>
<td>1250.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1250.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1657</td>
<td>BOTTOMSIDE[0]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOB27[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/u_ck_gen/PCLK</td>
</tr>
<tr>
<td>1250.548</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/u_ck_gen</td>
</tr>
<tr>
<td>1250.395</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOB27[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/u_ck_gen</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.208</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.001</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.197</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1252.592</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1250.395</td>
</tr>
<tr>
<td class="label">From</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1249.999</td>
<td>1249.999</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1249.999</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_clkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.546</td>
<td>0.548</td>
<td>tCL</td>
<td>RR</td>
<td>327</td>
<td>TOPSIDE[0]</td>
<td>u_clkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.790</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C24[0][A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK</td>
</tr>
<tr>
<td>1251.022</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1189</td>
<td>R34C24[0][A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1252.592</td>
<td>1.570</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>IOB35[A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1250.000</td>
<td>1250.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1250.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1657</td>
<td>BOTTOMSIDE[0]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOB35[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/PCLK</td>
</tr>
<tr>
<td>1250.548</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen</td>
</tr>
<tr>
<td>1250.395</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOB35[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.208</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.001</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.197</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1252.592</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1250.395</td>
</tr>
<tr>
<td class="label">From</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1249.999</td>
<td>1249.999</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1249.999</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_clkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.546</td>
<td>0.548</td>
<td>tCL</td>
<td>RR</td>
<td>327</td>
<td>TOPSIDE[0]</td>
<td>u_clkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.790</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C24[0][A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK</td>
</tr>
<tr>
<td>1251.022</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1189</td>
<td>R34C24[0][A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1252.592</td>
<td>1.570</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>IOB9[A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1250.000</td>
<td>1250.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1250.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1657</td>
<td>BOTTOMSIDE[0]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOB9[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/PCLK</td>
</tr>
<tr>
<td>1250.548</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen</td>
</tr>
<tr>
<td>1250.395</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOB9[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.208</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.001</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.197</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1252.592</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1250.395</td>
</tr>
<tr>
<td class="label">From</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1249.999</td>
<td>1249.999</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1249.999</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_clkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.546</td>
<td>0.548</td>
<td>tCL</td>
<td>RR</td>
<td>327</td>
<td>TOPSIDE[0]</td>
<td>u_clkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.790</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C24[0][A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK</td>
</tr>
<tr>
<td>1251.022</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1189</td>
<td>R34C24[0][A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1252.592</td>
<td>1.570</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>IOB26[A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1250.000</td>
<td>1250.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1250.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1657</td>
<td>BOTTOMSIDE[0]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOB26[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/PCLK</td>
</tr>
<tr>
<td>1250.548</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen</td>
</tr>
<tr>
<td>1250.395</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOB26[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.208</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.001</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.197</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1252.592</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1250.395</td>
</tr>
<tr>
<td class="label">From</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1249.999</td>
<td>1249.999</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1249.999</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_clkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.546</td>
<td>0.548</td>
<td>tCL</td>
<td>RR</td>
<td>327</td>
<td>TOPSIDE[0]</td>
<td>u_clkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.790</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C24[0][A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK</td>
</tr>
<tr>
<td>1251.022</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1189</td>
<td>R34C24[0][A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1252.592</td>
<td>1.570</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>IOL29[A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1250.000</td>
<td>1250.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1250.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1657</td>
<td>BOTTOMSIDE[0]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL29[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/PCLK</td>
</tr>
<tr>
<td>1250.548</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen</td>
</tr>
<tr>
<td>1250.395</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOL29[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.208</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.001</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.197</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1252.592</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1250.395</td>
</tr>
<tr>
<td class="label">From</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1249.999</td>
<td>1249.999</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1249.999</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_clkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.546</td>
<td>0.548</td>
<td>tCL</td>
<td>RR</td>
<td>327</td>
<td>TOPSIDE[0]</td>
<td>u_clkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.790</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C24[0][A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK</td>
</tr>
<tr>
<td>1251.022</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1189</td>
<td>R34C24[0][A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1252.592</td>
<td>1.570</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>IOB4[A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1250.000</td>
<td>1250.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1250.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1657</td>
<td>BOTTOMSIDE[0]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOB4[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/PCLK</td>
</tr>
<tr>
<td>1250.548</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen</td>
</tr>
<tr>
<td>1250.395</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOB4[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.208</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.001</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.197</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1252.592</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1250.395</td>
</tr>
<tr>
<td class="label">From</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1249.999</td>
<td>1249.999</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1249.999</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_clkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.546</td>
<td>0.548</td>
<td>tCL</td>
<td>RR</td>
<td>327</td>
<td>TOPSIDE[0]</td>
<td>u_clkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.790</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C24[0][A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK</td>
</tr>
<tr>
<td>1251.022</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1189</td>
<td>R34C24[0][A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1252.592</td>
<td>1.570</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>IOL40[A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1250.000</td>
<td>1250.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1250.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1657</td>
<td>BOTTOMSIDE[0]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL40[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen/PCLK</td>
</tr>
<tr>
<td>1250.548</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen</td>
</tr>
<tr>
<td>1250.395</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOL40[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.208</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.001</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.197</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1252.592</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1250.395</td>
</tr>
<tr>
<td class="label">From</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[16].u_cmd_gen</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1249.999</td>
<td>1249.999</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1249.999</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_clkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.546</td>
<td>0.548</td>
<td>tCL</td>
<td>RR</td>
<td>327</td>
<td>TOPSIDE[0]</td>
<td>u_clkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.790</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C24[0][A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK</td>
</tr>
<tr>
<td>1251.022</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1189</td>
<td>R34C24[0][A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1252.592</td>
<td>1.570</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>IOB36[A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[16].u_cmd_gen/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1250.000</td>
<td>1250.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1250.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1657</td>
<td>BOTTOMSIDE[0]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOB36[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[16].u_cmd_gen/PCLK</td>
</tr>
<tr>
<td>1250.548</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[16].u_cmd_gen</td>
</tr>
<tr>
<td>1250.395</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOB36[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[16].u_cmd_gen</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.208</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.001</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.197</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1252.592</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1250.395</td>
</tr>
<tr>
<td class="label">From</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[15].u_cmd_gen</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1249.999</td>
<td>1249.999</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1249.999</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_clkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.546</td>
<td>0.548</td>
<td>tCL</td>
<td>RR</td>
<td>327</td>
<td>TOPSIDE[0]</td>
<td>u_clkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.790</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C24[0][A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK</td>
</tr>
<tr>
<td>1251.022</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1189</td>
<td>R34C24[0][A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1252.592</td>
<td>1.570</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>IOL31[A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[15].u_cmd_gen/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1250.000</td>
<td>1250.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1250.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1657</td>
<td>BOTTOMSIDE[0]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL31[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[15].u_cmd_gen/PCLK</td>
</tr>
<tr>
<td>1250.548</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[15].u_cmd_gen</td>
</tr>
<tr>
<td>1250.395</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOL31[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[15].u_cmd_gen</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.208</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.001</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.197</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1252.592</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1250.395</td>
</tr>
<tr>
<td class="label">From</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[14].u_cmd_gen</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1249.999</td>
<td>1249.999</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1249.999</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_clkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.546</td>
<td>0.548</td>
<td>tCL</td>
<td>RR</td>
<td>327</td>
<td>TOPSIDE[0]</td>
<td>u_clkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.790</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C24[0][A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK</td>
</tr>
<tr>
<td>1251.022</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1189</td>
<td>R34C24[0][A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1252.592</td>
<td>1.570</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>IOB7[A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[14].u_cmd_gen/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1250.000</td>
<td>1250.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1250.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1657</td>
<td>BOTTOMSIDE[0]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOB7[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[14].u_cmd_gen/PCLK</td>
</tr>
<tr>
<td>1250.548</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[14].u_cmd_gen</td>
</tr>
<tr>
<td>1250.395</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOB7[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[14].u_cmd_gen</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.208</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.001</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.197</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1252.592</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1250.395</td>
</tr>
<tr>
<td class="label">From</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[13].u_cmd_gen</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1249.999</td>
<td>1249.999</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1249.999</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_clkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.546</td>
<td>0.548</td>
<td>tCL</td>
<td>RR</td>
<td>327</td>
<td>TOPSIDE[0]</td>
<td>u_clkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.790</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C24[0][A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK</td>
</tr>
<tr>
<td>1251.022</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1189</td>
<td>R34C24[0][A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1252.592</td>
<td>1.570</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>IOL38[A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[13].u_cmd_gen/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1250.000</td>
<td>1250.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1250.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1657</td>
<td>BOTTOMSIDE[0]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL38[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[13].u_cmd_gen/PCLK</td>
</tr>
<tr>
<td>1250.548</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[13].u_cmd_gen</td>
</tr>
<tr>
<td>1250.395</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOL38[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[13].u_cmd_gen</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.208</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.001</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.197</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1252.592</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1250.395</td>
</tr>
<tr>
<td class="label">From</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[12].u_cmd_gen</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1249.999</td>
<td>1249.999</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1249.999</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_clkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.546</td>
<td>0.548</td>
<td>tCL</td>
<td>RR</td>
<td>327</td>
<td>TOPSIDE[0]</td>
<td>u_clkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.790</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C24[0][A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK</td>
</tr>
<tr>
<td>1251.022</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1189</td>
<td>R34C24[0][A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1252.592</td>
<td>1.570</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>IOB8[A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[12].u_cmd_gen/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1250.000</td>
<td>1250.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1250.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1657</td>
<td>BOTTOMSIDE[0]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOB8[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[12].u_cmd_gen/PCLK</td>
</tr>
<tr>
<td>1250.548</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[12].u_cmd_gen</td>
</tr>
<tr>
<td>1250.395</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOB8[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[12].u_cmd_gen</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.208</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.001</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.197</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1252.592</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1250.395</td>
</tr>
<tr>
<td class="label">From</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[11].u_cmd_gen</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1249.999</td>
<td>1249.999</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1249.999</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_clkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.546</td>
<td>0.548</td>
<td>tCL</td>
<td>RR</td>
<td>327</td>
<td>TOPSIDE[0]</td>
<td>u_clkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.790</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C24[0][A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK</td>
</tr>
<tr>
<td>1251.022</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1189</td>
<td>R34C24[0][A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1252.592</td>
<td>1.570</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>IOL53[A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[11].u_cmd_gen/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1250.000</td>
<td>1250.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1250.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1657</td>
<td>BOTTOMSIDE[0]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL53[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[11].u_cmd_gen/PCLK</td>
</tr>
<tr>
<td>1250.548</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[11].u_cmd_gen</td>
</tr>
<tr>
<td>1250.395</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOL53[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[11].u_cmd_gen</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.208</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.001</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.197</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1252.592</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1250.395</td>
</tr>
<tr>
<td class="label">From</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[10].u_cmd_gen</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1249.999</td>
<td>1249.999</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1249.999</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_clkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.546</td>
<td>0.548</td>
<td>tCL</td>
<td>RR</td>
<td>327</td>
<td>TOPSIDE[0]</td>
<td>u_clkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.790</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C24[0][A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK</td>
</tr>
<tr>
<td>1251.022</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1189</td>
<td>R34C24[0][A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1252.592</td>
<td>1.570</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>IOL47[A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[10].u_cmd_gen/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1250.000</td>
<td>1250.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1250.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1657</td>
<td>BOTTOMSIDE[0]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL47[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[10].u_cmd_gen/PCLK</td>
</tr>
<tr>
<td>1250.548</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[10].u_cmd_gen</td>
</tr>
<tr>
<td>1250.395</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOL47[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[10].u_cmd_gen</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.208</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.001</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.197</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1252.592</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1250.395</td>
</tr>
<tr>
<td class="label">From</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1249.999</td>
<td>1249.999</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1249.999</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_clkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.546</td>
<td>0.548</td>
<td>tCL</td>
<td>RR</td>
<td>327</td>
<td>TOPSIDE[0]</td>
<td>u_clkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.790</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C24[0][A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK</td>
</tr>
<tr>
<td>1251.022</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1189</td>
<td>R34C24[0][A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1252.592</td>
<td>1.570</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>IOL35[A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1250.000</td>
<td>1250.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1250.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1657</td>
<td>BOTTOMSIDE[0]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL35[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen/PCLK</td>
</tr>
<tr>
<td>1250.548</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen</td>
</tr>
<tr>
<td>1250.395</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOL35[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.208</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.001</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.197</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1252.592</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1250.395</td>
</tr>
<tr>
<td class="label">From</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[8].u_cmd_gen</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1249.999</td>
<td>1249.999</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1249.999</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_clkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.546</td>
<td>0.548</td>
<td>tCL</td>
<td>RR</td>
<td>327</td>
<td>TOPSIDE[0]</td>
<td>u_clkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.790</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C24[0][A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK</td>
</tr>
<tr>
<td>1251.022</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1189</td>
<td>R34C24[0][A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1252.592</td>
<td>1.570</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>IOB3[A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[8].u_cmd_gen/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1250.000</td>
<td>1250.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1250.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1657</td>
<td>BOTTOMSIDE[0]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOB3[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[8].u_cmd_gen/PCLK</td>
</tr>
<tr>
<td>1250.548</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[8].u_cmd_gen</td>
</tr>
<tr>
<td>1250.395</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOB3[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[8].u_cmd_gen</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.208</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.001</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.197</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1252.592</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1250.395</td>
</tr>
<tr>
<td class="label">From</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[7].u_cmd_gen</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1249.999</td>
<td>1249.999</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1249.999</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_clkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.546</td>
<td>0.548</td>
<td>tCL</td>
<td>RR</td>
<td>327</td>
<td>TOPSIDE[0]</td>
<td>u_clkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.790</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C24[0][A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK</td>
</tr>
<tr>
<td>1251.022</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1189</td>
<td>R34C24[0][A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1252.592</td>
<td>1.570</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>IOB2[A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[7].u_cmd_gen/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1250.000</td>
<td>1250.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1250.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1657</td>
<td>BOTTOMSIDE[0]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOB2[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[7].u_cmd_gen/PCLK</td>
</tr>
<tr>
<td>1250.548</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[7].u_cmd_gen</td>
</tr>
<tr>
<td>1250.395</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOB2[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[7].u_cmd_gen</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.208</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.001</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.197</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1252.592</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1250.395</td>
</tr>
<tr>
<td class="label">From</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[6].u_cmd_gen</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_clkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1249.999</td>
<td>1249.999</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1249.999</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_clkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.546</td>
<td>0.548</td>
<td>tCL</td>
<td>RR</td>
<td>327</td>
<td>TOPSIDE[0]</td>
<td>u_clkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.790</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C24[0][A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK</td>
</tr>
<tr>
<td>1251.022</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1189</td>
<td>R34C24[0][A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1252.592</td>
<td>1.570</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>IOL45[A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[6].u_cmd_gen/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1250.000</td>
<td>1250.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1250.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1250.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1657</td>
<td>BOTTOMSIDE[0]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>1250.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL45[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[6].u_cmd_gen/PCLK</td>
</tr>
<tr>
<td>1250.548</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[6].u_cmd_gen</td>
</tr>
<tr>
<td>1250.395</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOL45[A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[6].u_cmd_gen</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.208</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.001</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.484</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.059</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.575</td>
</tr>
<tr>
<td class="label">From</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[3].ram_dfflr/qout_r_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.582</td>
<td>0.906</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C49[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/CLK</td>
</tr>
<tr>
<td>1.784</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>383</td>
<td>R8C49[1][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
</tr>
<tr>
<td>2.059</td>
<td>0.275</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C47[0][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[3].ram_dfflr/qout_r_5_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.564</td>
<td>0.889</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C47[0][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[3].ram_dfflr/qout_r_5_s0/CLK</td>
</tr>
<tr>
<td>1.575</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R4C47[0][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[3].ram_dfflr/qout_r_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.018</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 42.703%; route: 0.906, 57.297%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.275, 57.694%; tC2Q: 0.202, 42.306%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 43.182%; route: 0.889, 56.818%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.484</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.059</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.575</td>
</tr>
<tr>
<td class="label">From</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[3].ram_dfflr/qout_r_28_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.582</td>
<td>0.906</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C49[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/CLK</td>
</tr>
<tr>
<td>1.784</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>383</td>
<td>R8C49[1][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
</tr>
<tr>
<td>2.059</td>
<td>0.275</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C47[0][B]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[3].ram_dfflr/qout_r_28_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.564</td>
<td>0.889</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C47[0][B]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[3].ram_dfflr/qout_r_28_s0/CLK</td>
</tr>
<tr>
<td>1.575</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R4C47[0][B]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[3].ram_dfflr/qout_r_28_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.018</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 42.703%; route: 0.906, 57.297%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.275, 57.694%; tC2Q: 0.202, 42.306%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 43.182%; route: 0.889, 56.818%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.484</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.059</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.575</td>
</tr>
<tr>
<td class="label">From</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[1].ram_dfflr/qout_r_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.582</td>
<td>0.906</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C49[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/CLK</td>
</tr>
<tr>
<td>1.784</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>383</td>
<td>R8C49[1][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
</tr>
<tr>
<td>2.059</td>
<td>0.275</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C47[1][B]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[1].ram_dfflr/qout_r_1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.564</td>
<td>0.889</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C47[1][B]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[1].ram_dfflr/qout_r_1_s0/CLK</td>
</tr>
<tr>
<td>1.575</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R4C47[1][B]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[1].ram_dfflr/qout_r_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.018</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 42.703%; route: 0.906, 57.297%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.275, 57.694%; tC2Q: 0.202, 42.306%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 43.182%; route: 0.889, 56.818%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.484</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.059</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.575</td>
</tr>
<tr>
<td class="label">From</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[1].ram_dfflr/qout_r_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.582</td>
<td>0.906</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C49[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/CLK</td>
</tr>
<tr>
<td>1.784</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>383</td>
<td>R8C49[1][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
</tr>
<tr>
<td>2.059</td>
<td>0.275</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C47[1][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[1].ram_dfflr/qout_r_2_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.564</td>
<td>0.889</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C47[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[1].ram_dfflr/qout_r_2_s0/CLK</td>
</tr>
<tr>
<td>1.575</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R4C47[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[1].ram_dfflr/qout_r_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.018</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 42.703%; route: 0.906, 57.297%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.275, 57.694%; tC2Q: 0.202, 42.306%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 43.182%; route: 0.889, 56.818%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.508</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.059</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.551</td>
</tr>
<tr>
<td class="label">From</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[6].ram_dfflr/qout_r_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.582</td>
<td>0.906</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C49[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/CLK</td>
</tr>
<tr>
<td>1.784</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>383</td>
<td>R8C49[1][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
</tr>
<tr>
<td>2.059</td>
<td>0.275</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C48[1][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[6].ram_dfflr/qout_r_6_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.540</td>
<td>0.865</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C48[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[6].ram_dfflr/qout_r_6_s0/CLK</td>
</tr>
<tr>
<td>1.551</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R4C48[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[6].ram_dfflr/qout_r_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.041</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 42.703%; route: 0.906, 57.297%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.275, 57.694%; tC2Q: 0.202, 42.306%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 43.851%; route: 0.865, 56.149%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.508</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.059</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.551</td>
</tr>
<tr>
<td class="label">From</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[6].ram_dfflr/qout_r_13_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.582</td>
<td>0.906</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C49[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/CLK</td>
</tr>
<tr>
<td>1.784</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>383</td>
<td>R8C49[1][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
</tr>
<tr>
<td>2.059</td>
<td>0.275</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C48[1][B]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[6].ram_dfflr/qout_r_13_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.540</td>
<td>0.865</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C48[1][B]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[6].ram_dfflr/qout_r_13_s0/CLK</td>
</tr>
<tr>
<td>1.551</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R4C48[1][B]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[6].ram_dfflr/qout_r_13_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.041</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 42.703%; route: 0.906, 57.297%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.275, 57.694%; tC2Q: 0.202, 42.306%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 43.851%; route: 0.865, 56.149%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.508</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.059</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.551</td>
</tr>
<tr>
<td class="label">From</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[4].ram_dfflr/qout_r_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.582</td>
<td>0.906</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C49[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/CLK</td>
</tr>
<tr>
<td>1.784</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>383</td>
<td>R8C49[1][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
</tr>
<tr>
<td>2.059</td>
<td>0.275</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C48[0][B]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[4].ram_dfflr/qout_r_1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.540</td>
<td>0.865</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C48[0][B]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[4].ram_dfflr/qout_r_1_s0/CLK</td>
</tr>
<tr>
<td>1.551</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R4C48[0][B]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[4].ram_dfflr/qout_r_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.041</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 42.703%; route: 0.906, 57.297%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.275, 57.694%; tC2Q: 0.202, 42.306%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 43.851%; route: 0.865, 56.149%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.508</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.059</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.551</td>
</tr>
<tr>
<td class="label">From</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[4].ram_dfflr/qout_r_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.582</td>
<td>0.906</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C49[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/CLK</td>
</tr>
<tr>
<td>1.784</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>383</td>
<td>R8C49[1][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
</tr>
<tr>
<td>2.059</td>
<td>0.275</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C48[0][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[4].ram_dfflr/qout_r_6_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.540</td>
<td>0.865</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C48[0][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[4].ram_dfflr/qout_r_6_s0/CLK</td>
</tr>
<tr>
<td>1.551</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R4C48[0][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[4].ram_dfflr/qout_r_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.041</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 42.703%; route: 0.906, 57.297%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.275, 57.694%; tC2Q: 0.202, 42.306%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 43.851%; route: 0.865, 56.149%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.600</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.135</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.535</td>
</tr>
<tr>
<td class="label">From</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/read_dog_cnt_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1657</td>
<td>BOTTOMSIDE[0]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>0.524</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R43C20[2][A]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK</td>
</tr>
<tr>
<td>0.726</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>585</td>
<td>R43C20[2][A]</td>
<td style=" font-weight:bold;">DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
</tr>
<tr>
<td>1.135</td>
<td>0.409</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C21[0][A]</td>
<td style=" font-weight:bold;">Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/read_dog_cnt_4_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1657</td>
<td>BOTTOMSIDE[0]</td>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>0.524</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C21[0][A]</td>
<td>Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/read_dog_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>0.535</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R35C21[0][A]</td>
<td>Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/read_dog_cnt_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.409, 66.943%; tC2Q: 0.202, 33.057%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.652</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.395</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.742</td>
</tr>
<tr>
<td class="label">From</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/u_i_vld_sync/sync_gen[1].i_is_not_0.sync_dffr/qout_r_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.582</td>
<td>0.906</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C49[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/CLK</td>
</tr>
<tr>
<td>1.784</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>383</td>
<td>R8C49[1][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
</tr>
<tr>
<td>2.395</td>
<td>0.611</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C50[2][B]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/u_i_vld_sync/sync_gen[1].i_is_not_0.sync_dffr/qout_r_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.731</td>
<td>1.056</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C50[2][B]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/u_i_vld_sync/sync_gen[1].i_is_not_0.sync_dffr/qout_r_0_s0/CLK</td>
</tr>
<tr>
<td>1.742</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R12C50[2][B]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/u_i_vld_sync/sync_gen[1].i_is_not_0.sync_dffr/qout_r_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.149</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 42.703%; route: 0.906, 57.297%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.611, 75.144%; tC2Q: 0.202, 24.856%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 39.022%; route: 1.056, 60.978%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.652</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.395</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.742</td>
</tr>
<tr>
<td class="label">From</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/u_i_vld_sync/sync_gen[0].i_is_0.sync_dffr/qout_r_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.582</td>
<td>0.906</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C49[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/CLK</td>
</tr>
<tr>
<td>1.784</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>383</td>
<td>R8C49[1][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
</tr>
<tr>
<td>2.395</td>
<td>0.611</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C50[2][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/u_i_vld_sync/sync_gen[0].i_is_0.sync_dffr/qout_r_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.731</td>
<td>1.056</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C50[2][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/u_i_vld_sync/sync_gen[0].i_is_0.sync_dffr/qout_r_0_s0/CLK</td>
</tr>
<tr>
<td>1.742</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R12C50[2][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/u_i_vld_sync/sync_gen[0].i_is_0.sync_dffr/qout_r_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.149</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 42.703%; route: 0.906, 57.297%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.611, 75.144%; tC2Q: 0.202, 24.856%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 39.022%; route: 1.056, 60.978%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.670</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.037</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.367</td>
</tr>
<tr>
<td class="label">From</td>
<td>xcorr1/finished_temp1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>xcorr3/mul_add_result_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.211</td>
<td>1.536</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R44C50[1][B]</td>
<td>xcorr1/finished_temp1_s0/CLK</td>
</tr>
<tr>
<td>2.413</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>6</td>
<td>R44C50[1][B]</td>
<td style=" font-weight:bold;">xcorr1/finished_temp1_s0/Q</td>
</tr>
<tr>
<td>2.662</td>
<td>0.249</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R47C50[3][A]</td>
<td>mic_serial_inst/n150_s1/I0</td>
</tr>
<tr>
<td>2.897</td>
<td>0.235</td>
<td>tINS</td>
<td>RR</td>
<td>748</td>
<td>R47C50[3][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/n150_s1/F</td>
</tr>
<tr>
<td>3.037</td>
<td>0.140</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R47C50[0][A]</td>
<td style=" font-weight:bold;">xcorr3/mul_add_result_6_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.356</td>
<td>1.681</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R47C50[0][A]</td>
<td>xcorr3/mul_add_result_6_s0/CLK</td>
</tr>
<tr>
<td>2.367</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R47C50[0][A]</td>
<td>xcorr3/mul_add_result_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.145</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 30.549%; route: 1.536, 69.451%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.235, 28.464%; route: 0.389, 47.069%; tC2Q: 0.202, 24.467%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 28.668%; route: 1.681, 71.332%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.670</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.037</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.367</td>
</tr>
<tr>
<td class="label">From</td>
<td>xcorr1/finished_temp1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>xcorr3/mul_add_result_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.211</td>
<td>1.536</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R44C50[1][B]</td>
<td>xcorr1/finished_temp1_s0/CLK</td>
</tr>
<tr>
<td>2.413</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>6</td>
<td>R44C50[1][B]</td>
<td style=" font-weight:bold;">xcorr1/finished_temp1_s0/Q</td>
</tr>
<tr>
<td>2.662</td>
<td>0.249</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R47C50[3][A]</td>
<td>mic_serial_inst/n150_s1/I0</td>
</tr>
<tr>
<td>2.897</td>
<td>0.235</td>
<td>tINS</td>
<td>RR</td>
<td>748</td>
<td>R47C50[3][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/n150_s1/F</td>
</tr>
<tr>
<td>3.037</td>
<td>0.140</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R47C50[0][B]</td>
<td style=" font-weight:bold;">xcorr3/mul_add_result_9_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.356</td>
<td>1.681</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R47C50[0][B]</td>
<td>xcorr3/mul_add_result_9_s0/CLK</td>
</tr>
<tr>
<td>2.367</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R47C50[0][B]</td>
<td>xcorr3/mul_add_result_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.145</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 30.549%; route: 1.536, 69.451%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.235, 28.464%; route: 0.389, 47.069%; tC2Q: 0.202, 24.467%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 28.668%; route: 1.681, 71.332%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.670</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.037</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.367</td>
</tr>
<tr>
<td class="label">From</td>
<td>xcorr1/finished_temp1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>xcorr3/mul_add_max_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.211</td>
<td>1.536</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R44C50[1][B]</td>
<td>xcorr1/finished_temp1_s0/CLK</td>
</tr>
<tr>
<td>2.413</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>6</td>
<td>R44C50[1][B]</td>
<td style=" font-weight:bold;">xcorr1/finished_temp1_s0/Q</td>
</tr>
<tr>
<td>2.662</td>
<td>0.249</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R47C50[3][A]</td>
<td>mic_serial_inst/n150_s1/I0</td>
</tr>
<tr>
<td>2.897</td>
<td>0.235</td>
<td>tINS</td>
<td>RR</td>
<td>748</td>
<td>R47C50[3][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/n150_s1/F</td>
</tr>
<tr>
<td>3.037</td>
<td>0.140</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R47C50[2][B]</td>
<td style=" font-weight:bold;">xcorr3/mul_add_max_7_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.356</td>
<td>1.681</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R47C50[2][B]</td>
<td>xcorr3/mul_add_max_7_s0/CLK</td>
</tr>
<tr>
<td>2.367</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R47C50[2][B]</td>
<td>xcorr3/mul_add_max_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.145</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 30.549%; route: 1.536, 69.451%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.235, 28.464%; route: 0.389, 47.069%; tC2Q: 0.202, 24.467%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 28.668%; route: 1.681, 71.332%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.670</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.037</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.367</td>
</tr>
<tr>
<td class="label">From</td>
<td>xcorr1/finished_temp1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>xcorr3/mul_add_max_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.211</td>
<td>1.536</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R44C50[1][B]</td>
<td>xcorr1/finished_temp1_s0/CLK</td>
</tr>
<tr>
<td>2.413</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>6</td>
<td>R44C50[1][B]</td>
<td style=" font-weight:bold;">xcorr1/finished_temp1_s0/Q</td>
</tr>
<tr>
<td>2.662</td>
<td>0.249</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R47C50[3][A]</td>
<td>mic_serial_inst/n150_s1/I0</td>
</tr>
<tr>
<td>2.897</td>
<td>0.235</td>
<td>tINS</td>
<td>RR</td>
<td>748</td>
<td>R47C50[3][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/n150_s1/F</td>
</tr>
<tr>
<td>3.037</td>
<td>0.140</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R47C50[1][A]</td>
<td style=" font-weight:bold;">xcorr3/mul_add_max_8_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.356</td>
<td>1.681</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R47C50[1][A]</td>
<td>xcorr3/mul_add_max_8_s0/CLK</td>
</tr>
<tr>
<td>2.367</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R47C50[1][A]</td>
<td>xcorr3/mul_add_max_8_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.145</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 30.549%; route: 1.536, 69.451%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.235, 28.464%; route: 0.389, 47.069%; tC2Q: 0.202, 24.467%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 28.668%; route: 1.681, 71.332%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.670</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.037</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.367</td>
</tr>
<tr>
<td class="label">From</td>
<td>xcorr1/finished_temp1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>xcorr3/mul_add_max_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.211</td>
<td>1.536</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R44C50[1][B]</td>
<td>xcorr1/finished_temp1_s0/CLK</td>
</tr>
<tr>
<td>2.413</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>6</td>
<td>R44C50[1][B]</td>
<td style=" font-weight:bold;">xcorr1/finished_temp1_s0/Q</td>
</tr>
<tr>
<td>2.662</td>
<td>0.249</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R47C50[3][A]</td>
<td>mic_serial_inst/n150_s1/I0</td>
</tr>
<tr>
<td>2.897</td>
<td>0.235</td>
<td>tINS</td>
<td>RR</td>
<td>748</td>
<td>R47C50[3][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/n150_s1/F</td>
</tr>
<tr>
<td>3.037</td>
<td>0.140</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R47C50[2][A]</td>
<td style=" font-weight:bold;">xcorr3/mul_add_max_9_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.356</td>
<td>1.681</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R47C50[2][A]</td>
<td>xcorr3/mul_add_max_9_s0/CLK</td>
</tr>
<tr>
<td>2.367</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R47C50[2][A]</td>
<td>xcorr3/mul_add_max_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.145</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 30.549%; route: 1.536, 69.451%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.235, 28.464%; route: 0.389, 47.069%; tC2Q: 0.202, 24.467%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 28.668%; route: 1.681, 71.332%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.670</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.037</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.367</td>
</tr>
<tr>
<td class="label">From</td>
<td>xcorr1/finished_temp1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>xcorr3/mul_add_max_11_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.211</td>
<td>1.536</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R44C50[1][B]</td>
<td>xcorr1/finished_temp1_s0/CLK</td>
</tr>
<tr>
<td>2.413</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>6</td>
<td>R44C50[1][B]</td>
<td style=" font-weight:bold;">xcorr1/finished_temp1_s0/Q</td>
</tr>
<tr>
<td>2.662</td>
<td>0.249</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R47C50[3][A]</td>
<td>mic_serial_inst/n150_s1/I0</td>
</tr>
<tr>
<td>2.897</td>
<td>0.235</td>
<td>tINS</td>
<td>RR</td>
<td>748</td>
<td>R47C50[3][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/n150_s1/F</td>
</tr>
<tr>
<td>3.037</td>
<td>0.140</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R47C50[1][B]</td>
<td style=" font-weight:bold;">xcorr3/mul_add_max_11_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>2.356</td>
<td>1.681</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R47C50[1][B]</td>
<td>xcorr3/mul_add_max_11_s0/CLK</td>
</tr>
<tr>
<td>2.367</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R47C50[1][B]</td>
<td>xcorr3/mul_add_max_11_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.145</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 30.549%; route: 1.536, 69.451%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.235, 28.464%; route: 0.389, 47.069%; tC2Q: 0.202, 24.467%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 28.668%; route: 1.681, 71.332%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.676</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.400</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.724</td>
</tr>
<tr>
<td class="label">From</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.582</td>
<td>0.906</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C49[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/CLK</td>
</tr>
<tr>
<td>1.784</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>383</td>
<td>R8C49[1][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
</tr>
<tr>
<td>2.400</td>
<td>0.616</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C51[1][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_3_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.713</td>
<td>1.037</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C51[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_3_s0/CLK</td>
</tr>
<tr>
<td>1.724</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C51[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.131</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 42.703%; route: 0.906, 57.297%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.616, 75.295%; tC2Q: 0.202, 24.705%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 39.436%; route: 1.037, 60.564%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.676</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.400</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.724</td>
</tr>
<tr>
<td class="label">From</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.582</td>
<td>0.906</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C49[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/CLK</td>
</tr>
<tr>
<td>1.784</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>383</td>
<td>R8C49[1][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
</tr>
<tr>
<td>2.400</td>
<td>0.616</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C51[1][B]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_8_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.713</td>
<td>1.037</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C51[1][B]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_8_s0/CLK</td>
</tr>
<tr>
<td>1.724</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C51[1][B]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_8_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.131</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 42.703%; route: 0.906, 57.297%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.616, 75.295%; tC2Q: 0.202, 24.705%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 39.436%; route: 1.037, 60.564%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.676</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.400</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.724</td>
</tr>
<tr>
<td class="label">From</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.582</td>
<td>0.906</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C49[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/CLK</td>
</tr>
<tr>
<td>1.784</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>383</td>
<td>R8C49[1][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
</tr>
<tr>
<td>2.400</td>
<td>0.616</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C51[2][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_9_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.713</td>
<td>1.037</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C51[2][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_9_s0/CLK</td>
</tr>
<tr>
<td>1.724</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C51[2][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.131</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 42.703%; route: 0.906, 57.297%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.616, 75.295%; tC2Q: 0.202, 24.705%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 39.436%; route: 1.037, 60.564%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.676</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.400</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.724</td>
</tr>
<tr>
<td class="label">From</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_10_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.582</td>
<td>0.906</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C49[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/CLK</td>
</tr>
<tr>
<td>1.784</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>383</td>
<td>R8C49[1][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
</tr>
<tr>
<td>2.400</td>
<td>0.616</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C51[2][B]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_10_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.713</td>
<td>1.037</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C51[2][B]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_10_s0/CLK</td>
</tr>
<tr>
<td>1.724</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C51[2][B]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_10_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.131</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 42.703%; route: 0.906, 57.297%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.616, 75.295%; tC2Q: 0.202, 24.705%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 39.436%; route: 1.037, 60.564%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.682</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.400</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.718</td>
</tr>
<tr>
<td class="label">From</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_12_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.582</td>
<td>0.906</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C49[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/CLK</td>
</tr>
<tr>
<td>1.784</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>383</td>
<td>R8C49[1][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
</tr>
<tr>
<td>2.400</td>
<td>0.616</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C50[1][B]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_12_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.707</td>
<td>1.031</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C50[1][B]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_12_s0/CLK</td>
</tr>
<tr>
<td>1.718</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C50[1][B]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_12_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.125</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 42.703%; route: 0.906, 57.297%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.616, 75.295%; tC2Q: 0.202, 24.705%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 39.577%; route: 1.031, 60.423%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.682</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.400</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.718</td>
</tr>
<tr>
<td class="label">From</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_15_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.582</td>
<td>0.906</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C49[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/CLK</td>
</tr>
<tr>
<td>1.784</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>383</td>
<td>R8C49[1][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
</tr>
<tr>
<td>2.400</td>
<td>0.616</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C50[2][B]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_15_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.707</td>
<td>1.031</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C50[2][B]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_15_s0/CLK</td>
</tr>
<tr>
<td>1.718</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C50[2][B]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_15_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.125</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 42.703%; route: 0.906, 57.297%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.616, 75.295%; tC2Q: 0.202, 24.705%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 39.577%; route: 1.031, 60.423%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.682</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.400</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.718</td>
</tr>
<tr>
<td class="label">From</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_20_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.582</td>
<td>0.906</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C49[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/CLK</td>
</tr>
<tr>
<td>1.784</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>383</td>
<td>R8C49[1][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
</tr>
<tr>
<td>2.400</td>
<td>0.616</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C50[2][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_20_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.707</td>
<td>1.031</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C50[2][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_20_s0/CLK</td>
</tr>
<tr>
<td>1.718</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C50[2][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_20_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.125</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 42.703%; route: 0.906, 57.297%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.616, 75.295%; tC2Q: 0.202, 24.705%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 39.577%; route: 1.031, 60.423%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.682</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.400</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.718</td>
</tr>
<tr>
<td class="label">From</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_32_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.582</td>
<td>0.906</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C49[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/CLK</td>
</tr>
<tr>
<td>1.784</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>383</td>
<td>R8C49[1][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/q_s0/Q</td>
</tr>
<tr>
<td>2.400</td>
<td>0.616</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C50[1][A]</td>
<td style=" font-weight:bold;">Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_32_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4499</td>
<td>IOT27[A]</td>
<td>gowin_ibuf_clk/O</td>
</tr>
<tr>
<td>1.707</td>
<td>1.031</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C50[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_32_s0/CLK</td>
</tr>
<tr>
<td>1.718</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C50[1][A]</td>
<td>Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/qout_r_32_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.125</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 42.703%; route: 0.906, 57.297%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.616, 75.295%; tC2Q: 0.202, 24.705%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 39.577%; route: 1.031, 60.423%</td>
</tr>
</table>
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h3>MPW1</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.190</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.190</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_23_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_1_s0/Q</td>
</tr>
<tr>
<td>6.977</td>
<td>1.977</td>
<td>tNET</td>
<td>FF</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_23_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_1_s0/Q</td>
</tr>
<tr>
<td>11.168</td>
<td>1.168</td>
<td>tNET</td>
<td>RR</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_23_s0/CLK</td>
</tr>
</table>
<h3>MPW2</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.190</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.190</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_22_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_1_s0/Q</td>
</tr>
<tr>
<td>6.977</td>
<td>1.977</td>
<td>tNET</td>
<td>FF</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_22_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_1_s0/Q</td>
</tr>
<tr>
<td>11.168</td>
<td>1.168</td>
<td>tNET</td>
<td>RR</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_22_s0/CLK</td>
</tr>
</table>
<h3>MPW3</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.190</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.190</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_21_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_1_s0/Q</td>
</tr>
<tr>
<td>6.977</td>
<td>1.977</td>
<td>tNET</td>
<td>FF</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_21_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_1_s0/Q</td>
</tr>
<tr>
<td>11.168</td>
<td>1.168</td>
<td>tNET</td>
<td>RR</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_21_s0/CLK</td>
</tr>
</table>
<h3>MPW4</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.190</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.190</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_20_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_1_s0/Q</td>
</tr>
<tr>
<td>6.977</td>
<td>1.977</td>
<td>tNET</td>
<td>FF</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_20_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_1_s0/Q</td>
</tr>
<tr>
<td>11.168</td>
<td>1.168</td>
<td>tNET</td>
<td>RR</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_20_s0/CLK</td>
</tr>
</table>
<h3>MPW5</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.190</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.190</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_19_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_1_s0/Q</td>
</tr>
<tr>
<td>6.977</td>
<td>1.977</td>
<td>tNET</td>
<td>FF</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_19_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_1_s0/Q</td>
</tr>
<tr>
<td>11.168</td>
<td>1.168</td>
<td>tNET</td>
<td>RR</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_19_s0/CLK</td>
</tr>
</table>
<h3>MPW6</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.190</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.190</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_18_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_1_s0/Q</td>
</tr>
<tr>
<td>6.977</td>
<td>1.977</td>
<td>tNET</td>
<td>FF</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_18_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_1_s0/Q</td>
</tr>
<tr>
<td>11.168</td>
<td>1.168</td>
<td>tNET</td>
<td>RR</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_18_s0/CLK</td>
</tr>
</table>
<h3>MPW7</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.190</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.190</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_17_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_1_s0/Q</td>
</tr>
<tr>
<td>6.977</td>
<td>1.977</td>
<td>tNET</td>
<td>FF</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_17_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_1_s0/Q</td>
</tr>
<tr>
<td>11.168</td>
<td>1.168</td>
<td>tNET</td>
<td>RR</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_17_s0/CLK</td>
</tr>
</table>
<h3>MPW8</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.190</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.190</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_16_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_1_s0/Q</td>
</tr>
<tr>
<td>6.977</td>
<td>1.977</td>
<td>tNET</td>
<td>FF</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_16_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_1_s0/Q</td>
</tr>
<tr>
<td>11.168</td>
<td>1.168</td>
<td>tNET</td>
<td>RR</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_16_s0/CLK</td>
</tr>
</table>
<h3>MPW9</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.190</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.190</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_14_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_1_s0/Q</td>
</tr>
<tr>
<td>6.977</td>
<td>1.977</td>
<td>tNET</td>
<td>FF</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_14_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_1_s0/Q</td>
</tr>
<tr>
<td>11.168</td>
<td>1.168</td>
<td>tNET</td>
<td>RR</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_14_s0/CLK</td>
</tr>
</table>
<h3>MPW10</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.190</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.190</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_6_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_1_s0/Q</td>
</tr>
<tr>
<td>6.977</td>
<td>1.977</td>
<td>tNET</td>
<td>FF</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_6_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_1_s0/Q</td>
</tr>
<tr>
<td>11.168</td>
<td>1.168</td>
<td>tNET</td>
<td>RR</td>
<td>mic_serial_inst/mic_sample_inst2/data_r_r_6_s0/CLK</td>
</tr>
</table>
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
<table class="detail_table">
<tr>
<th class="label">FANOUT</th>
<th class="label">NET NAME</th>
<th class="label">WORST SLACK</th>
<th class="label">MAX DELAY</th>
</tr>
<tr>
<td>1657</td>
<td>dma_clk</td>
<td>-2.611</td>
<td>0.261</td>
</tr>
<tr>
<td>1189</td>
<td>ddr_rst</td>
<td>-3.413</td>
<td>1.813</td>
</tr>
<tr>
<td>748</td>
<td>n150_5</td>
<td>33.232</td>
<td>3.150</td>
</tr>
<tr>
<td>679</td>
<td>n556_5</td>
<td>8.302</td>
<td>2.578</td>
</tr>
<tr>
<td>585</td>
<td>init_calib_complete</td>
<td>0.655</td>
<td>2.128</td>
</tr>
<tr>
<td>545</td>
<td>decoded_rs[0]</td>
<td>24.435</td>
<td>1.849</td>
</tr>
<tr>
<td>327</td>
<td>video_clk</td>
<td>-82.587</td>
<td>0.261</td>
</tr>
<tr>
<td>289</td>
<td>decoded_rs[1]</td>
<td>23.545</td>
<td>2.836</td>
</tr>
<tr>
<td>205</td>
<td>finished_left_Z</td>
<td>33.050</td>
<td>3.233</td>
</tr>
<tr>
<td>185</td>
<td>cpu_state.cpu_state_ld_rs2</td>
<td>23.545</td>
<td>2.463</td>
</tr>
</table>
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
<h4>Report Command:report_route_congestion -max_grids 10</h4>
<table class="detail_table">
<tr>
<th class="label">GRID LOC</th>
<th class="label">ROUTE CONGESTIONS</th>
</tr>
<tr>
<td>R14C32</td>
<td>100.00%</td>
</tr>
<tr>
<td>R22C30</td>
<td>95.83%</td>
</tr>
<tr>
<td>R18C31</td>
<td>94.44%</td>
</tr>
<tr>
<td>R11C35</td>
<td>94.44%</td>
</tr>
<tr>
<td>R17C32</td>
<td>93.06%</td>
</tr>
<tr>
<td>R3C52</td>
<td>93.06%</td>
</tr>
<tr>
<td>R13C31</td>
<td>93.06%</td>
</tr>
<tr>
<td>R25C17</td>
<td>93.06%</td>
</tr>
<tr>
<td>R25C51</td>
<td>93.06%</td>
</tr>
<tr>
<td>R21C33</td>
<td>93.06%</td>
</tr>
</table>
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
<table class="detail_table">
<tr>
<th class="label">SDC Command Type</th>
<th class="label">State</th>
<th class="label">Detail Command</th>
</tr>
<tr>
<td>TC_CLOCK</td>
<td>Actived</td>
<td>create_clock -name clk       -period 37.037 [get_ports {clk}] -add</td>
</tr>
<tr>
<td>TC_CLOCK</td>
<td>Actived</td>
<td>create_clock -name cmos_pclk -period 10 [get_ports {cmos_pclk}] -add</td>
</tr>
<tr>
<td>TC_CLOCK</td>
<td>Actived</td>
<td>create_clock -name cmos_vsync -period 1000 [get_ports {cmos_vsync}] -add</td>
</tr>
<tr>
<td>TC_CLOCK</td>
<td>Actived</td>
<td>create_clock -name mem_clk -period 2.5 -waveform {0 1.25} [get_nets {memory_clk}]</td>
</tr>
<tr>
<td></td>
<td>Actived</td>
<td>report_timing -hold -from_clock [get_clocks {clk*}] -to_clock [get_clocks {clk*}] -max_paths 25 -max_common_paths 1</td>
</tr>
<tr>
<td></td>
<td>Actived</td>
<td>report_timing -setup -from_clock [get_clocks {clk*}] -to_clock [get_clocks {clk*}] -max_paths 25 -max_common_paths 1</td>
</tr>
</table>
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